參數(shù)資料
型號: AGLP125V5CSG281I
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA281
封裝: 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, ROHS COMPLIANT, CSP-281
文件頁數(shù): 98/128頁
文件大?。?/td> 4383K
代理商: AGLP125V5CSG281I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 57
Global Resource Characteristics
AGLP125 Clock Tree Topology
Clock delays are device-specific. Figure 2-21 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-21 is driven by a CCC located on the west side of the AGLP125 device.
It is used to drive all D-flip-flops in the device.
Figure 2-21 Example of Global Tree Use in an AGLP125 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
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AGLP125V5CSG281 FPGA, 3120 CLBS, 125000 GATES, PBGA281
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