2-62 Revision 16 Table 2-91 IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 Devices, 1.2 V " />
參數(shù)資料
型號： AGLP060V5-CS201
廠商： Microsemi SoC
文件頁數(shù)： 109/134頁
文件大小： 0K
描述： IC FPGA IGLOO PLUS 60K 201-CSP
標準包裝： 384
系列： IGLOO PLUS
邏輯元件/單元數(shù)： 1584
RAM 位總計： 18432
輸入/輸出數(shù)： 157
門數(shù)： 60000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 201-VFBGA，CSBGA
供應(yīng)商設(shè)備封裝： 201-CSP（8x8）
IGLOO PLUS DC and Switching Characteristics
2-62
Revision 16
Table 2-91 IGLOO PLUS CCC/PLL Specification
For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
160
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
160
MHz
Delay Increments in Programmable Delay Blocks 1, 2
5803
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL4,5
60
MHz
Input Cycle-to-Cycle Jitter (peak magnitude)
.25
ns
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter6
LockControl = 0
4
ns
LockControl = 1
3
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
2.3
20.86
ns
Delay Range in Block: Programmable Delay 2 1, 2
0.863
20.86
ns
Delay Range in Block: Fixed Delay 1, 2
5.7
ns
VCO Output Peak-to-Peak Period Jitter FCCC_OUT7
Maximum Peak-to-Peak Period Jitter7,8,9
SSO
2
SSO
4
SSO
8 SSO 16
0.75 MHz to 50 MHz
0.50%
1.20%
2.00%
3.00%
50 MHz to 160 MHz
2.50%
5.00%
7.00%
15.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. TJ = 25°C, VCC = 1.2 V
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the online help associated with the core for more information.
4. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions.For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
5. The AGLP030 device does not support PLL.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.
7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider
settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output
divider settings.
8. Measurements are done with LVTTL 3.3 V, 8 mA, I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
9. SSO are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ±200 ps of each
other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and
Printed Circuit Board Layout" section in the IGLOO PLUS FPGA Fabric User’s Guide
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