1-4 Revision 16 Flash*Freeze Technology The IGLOO PLUS device has an ultra-low power static mode, called " />
參數(shù)資料
型號: AGLP060V2-CSG201
廠商: Microsemi SoC
文件頁數(shù): 2/134頁
文件大小: 0K
描述: IC FPGA IGLOO PLUS 60K 201-CSP
標準包裝: 384
系列: IGLOO PLUS
邏輯元件/單元數(shù): 1584
RAM 位總計: 18432
輸入/輸出數(shù): 157
門數(shù): 60000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 201-VFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 201-CSP(8x8)
IGLOO PLUS Device Family Overview
1-4
Revision 16
Flash*Freeze Technology
The IGLOO PLUS device has an ultra-low power static mode, called Flash*Freeze mode, which retains
all SRAM and register information and can still quickly return to normal operation. Flash*Freeze
technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global
I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be
driven or can be toggling without impact on power consumption, and the device retains all core registers,
SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state
or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state using weak pull-
up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins,
or PLL, and the device consumes as little as 5 W in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. Refer to Figure 1-2 for an illustration of entering/exiting
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
Note: *Not supported by AGLP030 devices
Figure 1-1 IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030,
AGLP060, and AGLP125)
Figure 1-2 IGLOO PLUS Flash*Freeze Mode
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
VersaTile
CCC
I/Os
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 0
Bank
1
Bank
1
Bank
3
Bank
3
Bank 2
*
IGLOO PLUS
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
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