Revision 17 2-25 The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. Th" />
參數(shù)資料
型號： AGLN125V2-CSG81I
廠商： Microsemi SoC
文件頁數(shù)： 87/150頁
文件大?。?/td> 0K
描述： IC FPGA NANO 1KB 125K 81-CSP
標(biāo)準(zhǔn)包裝： 640
系列： IGLOO nano
邏輯元件/單元數(shù)： 3072
RAM 位總計： 36864
輸入/輸出數(shù)： 60
門數(shù)： 125000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 81-WFBGA，CSBGA
供應(yīng)商設(shè)備封裝： 81-CSP（5x5）
IGLOO nano Low Power Flash FPGAs
Revision 17
2-25
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-31 Duration of Short Circuit Event before Failure
Temperature
Time before Failure
–40°C
> 20 years
–20°C
> 20 years
0°C
> 20 years
25°C
> 20 years
70°C
5 years
85°C
2 years
100°C
6 months
Table 2-32 Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL / LVCMOS (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
1.2 V LVCMOS (Schmitt trigger mode)
40 mV
Table 2-33 I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall
Time (min.)
Input Rise/Fall Time
(max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns *
20 years (100°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but
input noise voltage
cannot exceed Schmitt
hysteresis.
20 years (100°C)
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board
noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure
that there is no excessive noise coupling into input signals.
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