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參數(shù)資料
| 型號(hào)： | AGLN010V2-QNG48I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 49/150頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA NANO 1KB 10K 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | IGLOO nano |
| 邏輯元件/單元數(shù)： | 260 |
| 輸入/輸出數(shù)： | 34 |
| 門數(shù)： | 10000 |
| 電源電壓： | 1.14 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（6x6） |
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Datasheet Information
5-2
Revision 17
Revision 12
(continued)
The "Specifying I/O States During Programming" section is new (SAR 34694).
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture"
section of the Global Resources chapter in the IGLOO nano FPGA Fabric User's
Guide (SAR 34732).
Figure 2-4 has been modified for DIN waveform; the Rise and Fall time label has been
changed to tDIN (37106).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated
to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software
Settings" section (SAR 34885).
2-26,
The notes regarding drive strength in the "Summary of I/O Timing Characteristics –
LVCMOS Wide Range" section tables were revised for clarification. They now state that
the minimum drive strength for the default software configuration when run in wide range
is ±100 A. The drive strength displayed in software is supported in normal range only.
For a detailed I/V curve, refer to the IBIS models (SAR 34765).
2-20,
Added values for minimum pulse width and removed the FRMAX row from Table 2-88
through Table 2-99 in the "Global Tree Timing Characteristics" section. Use the software
to determine the FRMAX for the device you are using (SAR 36953).
2-64 to
CCC/PLL Specification were updated. A note was added indicating that when the
CCC/PLL core is generated by Mircosemi core generator software, not all delay values
of the specified delay increments are available (SAR 34817).
and
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-36 FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SAR 35754).
Reference was made to a new application note, Simultaneous Read-Write Operations in
Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail
(SAR 34865).
2-74,
The "Pin Descriptions" chapter has been added (SAR 34770).
Package names used in the "Package Pin Assignments" section were revised to match
standards given in Package Mechanical Drawings (SAR 34770).
Revision 11
(Jul 2010)
The status of the AGLN060 device has changed from Advance to Production.
The values for PAC1, PAC2, PAC3, and PAC4 were updated in Table 2-15 Different
1.5 V core supply voltage (SAR 26404).
The values for PAC1, PAC2, PAC3, and PAC4 were updated in Table 2-17 Different
1.2 V core supply voltage (SAR 26404).
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "IGLOO nano
Device Status" table on page II indicates the status for each device in the device family.
N/A
Revision
Changes
Page
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| AGLN010V2-UCG36 | 功能描述:IC FPGA 10K 1.2-1.5V 36UCG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO nano 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| AGLN010V2-UCG36I | 功能描述:IC FPGA NANO 1KB 10K 36-UCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
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