參數(shù)資料
型號(hào): AGLE600V2-FFG484C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數(shù): 6/156頁
文件大?。?/td> 5023K
代理商: AGLE600V2-FFG484C
IGLOOe DC and Switching Characteristics
Ad vance v0.3
2-89
Global Resource Characteristics
AGLE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-39 is an example of a global tree used for clock routing.
The global tree presented in Figure 2-39 is driven by a CCC located on the west side of the AGLE600
device. It is used to drive all D-flip-flops in the device.
Figure 2-39 Example of Global Tree Use in an AGLE600 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
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