Fusion Family of Mixed Signal FPGAs
Revision 4
2-193
Table 2-122 1.8 V LVCMOS Low Slew
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 1.7 V
Applicable to Advanced I/Os
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.66
15.53
0.04
1.31
0.43
14.11 15.53
2.78
1.60
16.35 17.77
ns
–1
0.56
13.21
0.04
1.11
0.36
12.01 13.21
2.36
1.36
13.91 15.11
ns
–22
0.49
11.60
0.03
0.98
0.32
10.54 11.60
2.07
1.19
12.21 13.27
ns
4 mA
Std.
0.66
10.48
0.04
1.31
0.43
10.41 10.48
3.23
2.73
12.65 12.71
ns
–1
0.56
8.91
0.04
1.11
0.36
8.86
8.91
2.75
2.33
10.76 10.81
ns
–2
0.49
7.82
0.03
0.98
0.32
7.77
7.82
2.41
2.04
9.44
9.49
ns
8 mA
Std.
0.66
8.05
0.04
1.31
0.43
8.20
7.84
3.54
3.27
10.43 10.08
ns
–1
0.56
6.85
0.04
1.11
0.36
6.97
6.67
3.01
2.78
8.88
8.57
ns
–2
0.49
6.01
0.03
0.98
0.32
6.12
5.86
2.64
2.44
7.79
7.53
ns
12 mA
Std.
0.66
7.50
0.04
1.31
0.43
7.64
7.30
3.61
3.41
9.88
9.53
ns
–1
0.56
6.38
0.04
1.11
0.36
6.50
6.21
3.07
2.90
8.40
8.11
ns
–2
0.49
5.60
0.03
0.98
0.32
5.71
5.45
2.69
2.55
7.38
7.12
ns
16 mA
Std.
0.66
7.29
0.04
1.31
0.43
7.23
7.29
3.71
3.95
9.47
9.53
ns
–1
0.56
6.20
0.04
1.11
0.36
6.15
6.20
3.15
3.36
8.06
8.11
ns
–2
0.49
5.45
0.03
0.98
0.32
5.40
5.45
2.77
2.95
7.07
7.12
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on