參數(shù)資料
型號: AFE1115E
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No
中文描述: HDSL / MDSL模擬前端與石英振蕩器
文件頁數(shù): 6/12頁
文件大小: 219K
代理商: AFE1115E
6
AFE1115
THEORY OF OPERATION
The transmit channel consists of a switched-capacitor pulse
forming network followed by a differential line driver. The
pulse forming network receives symbol data through a serial
interface and generates a standard 2B1Q output waveform.
The output meets the pulse mask and power spectral density
requirements defined in European Telecommunications Stan-
dards Institute document RTR/TM-03036 for E1 mode and
in sections 6.2.1 and 6.2.2.1 of Bellcore technical advisory
TA-NWT-001210 for T1 mode. The differential line driver
uses a composite output stage combining class B operation
(for high efficiency driving large signals) with class AB
operation (to minimize crossover distortion).
The receive channel is designed around a fourth-order delta
sigma A/D converter. It includes a difference amplifier
designed to be used with an external compromise hybrid for
first order analog echo cancellation. A programmable gain
amplifier with gains of –3dB to +9dB is also included. The
delta sigma modulator operating at a 24X oversampling ratio
produces a parallel 14-bit output at symbol rates up to
584kHz. The basic functionality of the AFE1115 is illus-
trated in Figure 1 shown below.
The receive channel operates by summing the two differen-
tial inputs, one from the line (rxLINE) and the other from the
compromise hybrid (rxHYB). These two inputs are con-
nected so that the hybrid signal is subtracted from the line
signal. This connection is described in the paragraph titled
“Echo Cancellation in the AFE”. The equivalent gain for
each input in the difference amp is one. The resulting signal
then passes to a programmable gain amplifier which can be
set for gains of –3dB through +9dB. The ADC converts the
signal to a 14-bit digital word, rxD13-rxD0.
An independent VCXO control DAC and VCXO circuitry is
also included on the chip. This VCXO is designed to be used
in remote units for clock recovery. The VCXO is formed
with the on-board circuitry plus external crystal and varactor
diodes. The VCXO control DAC receives control data through
a serial interface which sets a voltage level at the output of
the DAC. The DAC output controls the frequency of the
VCXO. To achieve specified analog performance when
using the VCXO, the crystal frequency of the VCXO must
be 48x the baud rate.
rxLOOP INPUT
rxLOOP is the loopback control signal. When enabled, the
rxLINE+ and rxLINE– inputs are disconnected from the
AFE. The rxHYB+ and rxHYB– inputs remain connected.
Loopback is enabled by applying a positive signal (Logic 1)
to rxLOOP.
ECHO CANCELLATION IN THE AFE
The rxHYB input is designed to be subtracted from the
rxLINE input for first order echo cancellation. To accom-
plish this, note that the rxLINE input is connected to the
same polarity signal at the transformer (positive to positive
and negative to negative) while the rxHYB input is con-
nected to opposite polarity through the compromise hybrid
(negative to positive and positive to negative) as shown in
Figure 2.
RECEIVE DATA CODING
The data from the receive channel A/D converter is coded in
two’s complement.
FIGURE 1. Functional Block Diagram of AFE1115 Circuit.
ANALOG INPUT
OUTPUT CODE (rxDATA)
Positive Full Scale
Mid Scale
Negative Full Scale
01111111111111
00000000000000
10000000000000
Σ
ADC
Switched Capacitor
Pulse Former
Programmable
Gain Amp
Difference
Amplifier
Digital
Filter
AFE1115
Line Driver
PLL
DSP
vcDATA
vcSCLK
vcLE
VCXO
DAC
vcDAC
VCXO Output
VCXO Input
VCXO
Hybrid
VCXO Output Clock
Telephone
Wire Pair
Transformer
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