參數(shù)資料
型號(hào): AFE1115
元件分類(lèi): 圓形連接器
英文描述: Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No
中文描述: HDSL / MDSL模擬前端與石英振蕩器
文件頁(yè)數(shù): 9/12頁(yè)
文件大?。?/td> 219K
代理商: AFE1115
9
AFE1115
TRANSMIT SYMBOL DATA
During each symbol period transmit symbol data are sent to
the AFE1115 in serial format through the txDATA input pin.
A 16 bit word is sent to the AFE1115 to determine the
symbol that is transmitted by the AFE1115. The symbol data
is contained in the first three bits of the data, the remaining
13 bits of the 16 bit word are ignored.
The most significant bit (MSB) is the transmit enable bit.
When the MSB is a logic 0, a zero symbol only is transmit-
ted regardless of the state of the other two bits. When the
MSB is a logic 1, bits 2 and 3 determine the symbol
transmitted as shown in the table below.
VCXO CONTROL D/A CONVERTER DATA
During each symbol period VCXO control D/A converter
data is sent to the AFE1115 in serial format through the
vcDATA input pin. A 16 bit word is sent to the AFE1115 to
determine the output of the VCXO control D/A converter.
The VCXO control D/A converter is connected to the
VCXO circuit to control the VCXO frequency. The D/A
converter input is contained in the first eight bits of the data,
the remaining eight bits of the 16 bit word are ignored.
MSB - BIT 1
BIT 2
BIT 3
2B1Q SYMBOL
0
1
1
1
1
X
1
1
0
0
X
1
0
1
0
O
+3
+1
–1
–3
TABLE I. Transmit Symbol Data (txDATA). X = Don’t Care.
INPUT CODE (vcDATA)
MSB
ANALOG OUTPUT
01111111XXXXXXXX
00000000XXXXXXXX
10000000XXXXXXXX
Negative Full Scale (+0.5V)
Mid Scale (+2.5V)
Positive Full Scale (+4.5V)
TABLE II. VCXO Control DAC Output. X = Don’t Care.
t
16
T = one symbol period
t
15
t
11
t
12
t
13
t
10
t
14
t
14
txCLK
RECEIVE TIMING
rxSYNC
rxDATA
t
14
t
14
Data 1a
Data 1
Data 2
NOTES: (1) rxSYNC can shift to one of 48 discrete delay times from the leading edge of txCLK. (2) Timing
is valid for load capacitance of 10pF or less. (3) It is recommended that rxDATA is read on the rising edge of
rxSYNC. (4) Data 1a is an interpolated value between Data 1 and Data 2.
FIGURE 5. Receive Timing Diagram.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
VALUE
t
10
t
11
t
12
t
13
t
14
t
15
t
16
rxSYNC Pulse Width
Delay of rxSYNC from rising edge of txCLK, n = 0 to 47
Nominal Time at Which rxDATA Changes from Data 1 to Data 1a
Nominal Time at Which rxDATA Changes from Data 1a to Data 2
Uncertainty of t12 and t13
txCLK Pulse Width
Symbol Period, T
T/24
nT/48 – T/96
nT/48 + T/96
(n + 1.5) T/48
(n + 25.5) T/48
20
ns
T/16
1.7
15T/16
10.2
μ
s
TABLE III. Receive Timing (n = Delay Increments from txCLK).
相關(guān)PDF資料
PDF描述
AFE1115E Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No
AFE1124 LJT 12C 8#20 4#16 SKT WALL REC
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AFE1144 Circular Connector; No. of Contacts:15; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 RoHS Compliant: No
AFE1144E Circular Connector; No. of Contacts:15; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AFE1115E/1K 功能描述:IC ANALOG FRONT END 56-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率(瓦特):- 電壓 - 電源,模擬:3 V ~ 3.6 V 電壓 - 電源,數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN(5x5) 包裝:帶卷 (TR)
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