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參數(shù)資料
| 型號(hào)： | AFE1104E |
| 英文描述： | HDSL/MDSL ANALOG FRONT END |
| 中文描述： | HDSL / MDSL模擬前端 |
| 文件頁數(shù)： | 10/10頁 |
| 文件大小： | 203K |
| 代理商： | AFE1104E |
10
AFE1104
The power dissipation listed in the specifications section
applies under these normal operating conditions: 5V Analog
Power Supply; 3.3V Digital Power Supply; standard 13.5dBm
delivered to the line; and a pseudo-random equiprobable
sequence of HDSL output pulses. The power dissipation
specifications includes all power dissipated in the AFE1104,
it does not include power dissipated in the external load.
The external power is 16.5dBm, 13.5dBm to the line and
13.5dBm to the impedance matching resistors. The external
load power of 16.5dBm is 45mW. The typical power dissi-
pation in the AFE1104 under various conditions is shown in
Table I.
pins of the AFE11104 (pins 3 through 26). However, DV
DD
may be supplied by a wide printed circuit board (PCB) trace.
A digital ground plane underneath all digital pins is strongly
recommended.
The phase-locked loop is powered from PV
DD
(pin 2) and its
ground is referenced to PGND (pin 1). Note that PV
DD
must
be in the 4.75V to 5.25V range. This portion of the AFE1104
should be decoupled with both a 10
μ
F Tantalum capacitor
and a 0.1
μ
F ceramic capacitor. The ceramic capacitor should
be placed as close to the AFE1104 as possible. The place-
ment of the Tantalum capacitor is not as critical, but should
be close. In each case, the capacitor should be connected
between PV
DD
and PGND.
In most systems, it will be natural to derive PV
DD
from the
AV
DD
supply. A 5
to 10
resistor should be used to
connect PV
DD
to the analog supply. This resistor in combi-
nation with the 10
μ
F capacitor form a lowpass filter—
keeping glitches on AV
DD
from affecting PV
DD
. Ideally,
PV
DD
would originate from the analog supply (via the
resistor) near the power connector for the printed circuit
board. Likewise, PGND should connect to a large PCB trace
or small ground plane which returns to the power supply
connector underneath the PV
DD
supply path. The PGND
“ground plane” should also extend underneath PLL
IN
and
PLL
OUT
(pins 47 and 48).
The remaining portion of the AFE1104 should be considered
analog. All AGND pins should be connected directly to a
common analog ground plane and all AV
DD
pins should be
connected to an analog 5V power plane. Both of these planes
should have a low impedance path to the power supply.
Ideally, all ground planes and traces and all power planes
and traces should return to the power supply connector
before being connected together (if necessary). Each ground
and power pair should be routed over each other, should not
overlap any portion of another pair, and the pairs should be
separated by a distance of at least 0.25 inch (6mm). One
exception is that the digital and analog ground planes should
be connected together underneath the AFE1104 by a small
trace.
TYPICAL POWER
DISSIPATION
IN THE AFE1104
(mW)
BIT RATE
PER AFE1104
(Symbols/sec)
DVDD
(V)
584 (E1)
584 (E1)
392 (T1)
392 (T1)
146 (E1/4)
146 (E1/4)
3.3
5
3.3
5
3.3
5
250
300
240
270
230
245
TABLE I. Typical Power Dissipation.
LAYOUT
The analog front end of an HDSL system has a number of
conflicting requirements. It must accept and deliver digital
outputs at fairly high rates of speed, phase-lock to a high-
speed digital clock, and convert the line input to a high-
precision (14-bit) digital output. Thus, there are really three
sections of the AFE1104: the digital section, the phase-
locked loop, and the analog section.
The power supply for the digital section of the AFE1104 can
range from 3.3V to 5V. This supply should be decoupled to
digital ground with a ceramic 0.1
μ
F capacitor placed as
close to DGND (pin 12) and DV
DD
(pin 13) as possible.
Ideally, both a digital power supply plane and a digital
ground plane should run up to and underneath the digital
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFE1105 | LJT 12C 8#20 4#16 SKT WALL REC |
| AFE1105E | Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No |
| AFE1115 | Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No |
| AFE1115E | Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No |
| AFE1124 | LJT 12C 8#20 4#16 SKT WALL REC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1104E/1K | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1104E/1KG4 | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1104EG4 | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1105 | 制造商:BB 制造商全稱:BB 功能描述:HDSL/MDSL ANALOG FRONT END |
| AFE1105E | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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