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參數(shù)資料
| 型號(hào)： | AFCT-5942AGZ |
| 元件分類： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 1260-1570nm, 2488Mbps(Tx), 2488Mbps(Rx), BOARD/PANEL MOUNT, DIP, LC CONNECTOR |
| 封裝： | ROHS COMPLIANT, DIP-20 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 557K |
| 代理商： | AFCT-5942AGZ |
7
Figure 6. Recommended Interface Circuit
Application Information
The Applications Engineering Group at Avago Tech-
nologies is available to assist you with technical under-
standing and design trade-offs associated with these
transceivers. You can contact them through your Avago
Technologies sales representative.
The following information is provided to answer some of
the most common questions about the use of the parts.
Optical Power Budget and Link Penalties
The worst-case Optical Power Budget (OPB) in dB for a
fiber-optic link is determined by the difference between
the minimum transmitter output optical power (dBm avg)
and the lowest receiver sensitivity (dBm avg). This OPB
provides the necessary optical signal range to establish a
working fiber-optic link. The OPB is allocated for the fiber-
optic cable length and the corresponding link penalties.
For proper link performance, all penalties that affect the
link performance must be accounted for within the link
optical power budget.
Electrical and Mechanical Interface
Recommended Circuit
Figure 6 shows the recommended interface for deploying
the Avago Technologies transceivers in a +3.3 V system.
o
Vp
dR
o
V
EE
RX
o
V
EE
RX
o
DN
C
o
D
N
C
o
V
EE
RX
o
V
CC
RX
o
SD
o
RD
-
o
RD
+
Z= 50
Z= 50
Z= 50
Z= 50
SD
LVTTL
V
CC (+3.3 V)
V
CC (+3.3 V)
RD+
RD-
1
P
M
O
N+
o
P
M
O
N-
o
B
M
O
N+
o
B
M
O
N-
o
V
EE
TX
o
TD
-
o
TD
+
o
T D
IS
o
V
EE
TX
o
V
CC
TX
o
1
H
C2
1
H
C1
C3
10
F
T
X
R
X
100
130
130
V
CCRX (+3.3 V)
P
MON+
P
MON-
B
MON+
B
MON-
T
DIS (LVTTL)
2
3
4 5
6
7
8
9 10
20 19 18 17 16 15 14 13 12 11
TD-
TD+
Note: C1 = C2 = C3 = 10 nF or 100 nF
TD+, TD- INPUTS ARE INTERNALLY TERMINATED AND AC COUPLED.
RD+, RD- OUTPUTS ARE INTERNALLY BIASED AND AC COUPLED.
Note A: CIRCUIT ASSUMES OPEN EMITTER OUTPUT.
Note B: CIRCUIT ASSUMES HIGH IMPENDANCE INTERNAL BIAS @ V
CC - 1.3 V.
Note C: THE BIAS RESISTOR FOR VpdR SHOULD NOT EXCEED 2 k
2 k
3 k
10 nF
NOTE A
NOTE B
V
CC (+3.3 V)
NOTE C
10
F
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