參數(shù)資料
型號： AF180C51C-36D
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 164/170頁
文件大小： 4133K
代理商： AF180C51C-36D
93
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Com-
plete Interrupt is requested if the ADIE bit is set. ADIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.
Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one, the ADC Conversion Complete Interrupt request is enabled.
Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the ADC.
13.12.3
ADCSRB
– ADC Control and Status Register B
Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of
the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching
to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
.
Table 13-3.
ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
00
0
2
00
1
2
01
0
4
01
1
8
10
0
16
10
1
32
11
0
64
11
1
128
Bit
7
65
432
10
–
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R
R/W
Initial Value
0
00
000
00
Table 13-4.
ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
0
Free Running mode
0
1
Analog Comparator
0
1
0
External Interrupt Flag 0
0
1
Timer/Counter 0 Compare Match A
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