參數(shù)資料
型號: ADW71205WSTZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC RDC 12BIT W/REF OSC 44LQFP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 12
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 50mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-LQFP(10x10)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
AD2S1205
Rev. A | Page 13 of 20
RD Input
CS Input
The 12-bit data bus lines are normally in a high impedance
state. The output buffer is enabled when CS and RD are held
low. A falling edge of the RD signal transfers data to the output
buffer. The selected data is made available to the bus to be read
within t6 of the RD pin going low. The data pins return to a high
impedance state when the RD pin returns to a high state within
t7. When reading data continuously, wait a minimum of t3 after
RD is released before reapplying it.
The device is enabled when CS is held low.
RDVEL Input
RDVEL input is used to select between the angular position
register and the angular velocity register, as shown in
RDVEL is held high to select the angular position register and
low to select the angular velocity register. The RDVEL pin must
be set (stable) at least t4 before the RD pin is pulled low.
06
33
9-
0
07
t3
t6
t7
fCLKIN
CLKIN
DATA
DON'T CARE
VELOCITY
POSITION
t2
SAMPLE
CS
RD
RDVEL
t1
t3
t5
t4
t5
t4
t7
t6
Figure 7. Parallel Port Read Timing
Table 6. Parallel Port Timing
Parameter
Description
Min
Typ
Max
Unit
fCLKIN
Frequency of clock input
6.144
8.192
10.24
MHz
t1
SAMPLE pulse width
2 × (1/fCLKIN) + 20
ns
t2
Delay from SAMPLE before RD/CS low
6 × (1/fCLKIN) + 20
ns
t3
RD pulse width
18
ns
t4
Set time RDVEL before RD/CS low
5
ns
t5
Hold time RDVEL after RD/CS low
7
ns
t6
Enable delay RD/CS low to data valid
30
ns
t7
Disable delay RD/CS low to data high-Z
18
ns
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