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參數(shù)資料
| 型號： | ADV7403 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| 中文描述： | 12位，綜合，多格式標(biāo)清/高清視頻解碼器和RGB圖形數(shù)字化儀 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 259K |
| 代理商： | ADV7403 |
ADV7403
TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 3.
Parameter
1, ,
Symbol
Test Conditions
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range
4
I
2
C PORT
5
SCLK Frequency
SCLK Min Pulse Width High
t
1
SCLK Min Pulse Width Low
t
2
Hold Time (Start Condition)
t
3
Setup Time (Start Condition)
t
4
SDA Setup Time
t
5
SCLK and SDA Rise Time
t
6
SCLK and SDA Fall Time
t
7
Setup Time for Stop Condition
t
8
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
t
9
:t
10
Rev. SpA | Page 7 of 24
2 3
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
5
45:55
Typ
28.63636
0.6
Max
±50
110
140
400
300
300
55:45
Unit
MHz
ppm
kHz
MHz
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty
cycle
ns
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)
6
t
11
Negative clock edge to start of
valid data
End of valid data to negative
clock edge
End of valid data to negative
clock edge
Negative clock edge to start of
valid data
Positive clock edge to end of
valid data
Positive clock edge to start of
valid data
Negative clock edge to end of
valid data
Negative clock edge to start of
valid data
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
DE_IN, data inputs
3.6
Data Output Transition Time SDR (SDP)
6
t
12
2.4
ns
Data Output Transition Time SDR (CP)
7
t
13
2.8
ns
Data Output Transition Time SDR (CP)
7
t
14
0.1
ns
Data Output Transition Time DDR (CP)
7, 8
t
15
4 + TLLC1/4
ns
Data Output Transition Time DDR (CP)
7, 8
t
16
0.25 + TLLC1/4
ns
Data Output Transition Time DDR (CP)
7, 8
t
17
2.95 + TLLC1/4
ns
Data Output Transition Time DDR (CP)
7, 8
t
18
0.5 + TLLC1/4
ns
DATA and CONTROL INPUTS
5
Input Setup Time (Digital Input Port)
Input Hold Time (Digital Input Port)
t
19
t
20
9
2.2
7
2
ns
ns
ns
ns
1
The min/max specifications are guaranteed over this range.
2
Temperature range T
MIN
to T
MAX
: 40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
3
Guaranteed by characterization.
4
Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.
5
TTL input values are 0 V to 3 V, with rise/fall times
≥
3 ns, measured between the 10% and 90% points.
6
SDP timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4.
7
CP timing figures obtained using max drive strength value (0xFF) in Register Subaddress 0xF4.
8
DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
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PDF描述 |
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| ADV7403BSTZ-110 | 12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7403BSTZ-1102 | 12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7403KSTZ-140 | 12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7403KSTZ-1402 | 12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADVHC32 | Voltage-to-Frequency and Frequency-to-Voltage Converter(電壓-頻率和頻率-電壓轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7403BSTZ-110 | 功能描述:視頻 IC 12-bit 110MHz MultFmtVidDecod I.C. RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7403BSTZ-110 | 制造商:Analog Devices 功能描述:IC 12-BIT VIDEO DECODER |
| ADV7403BSTZ-1102 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7403CSTZ-110 | 制造商:Analog Devices 功能描述: |
| ADV7403CSTZ-140 | 制造商:Analog Devices 功能描述: |
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