VDD
參數(shù)資料
型號(hào): ADV7393BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 12/108頁(yè)
文件大?。?/td> 0K
描述: IC DAC VIDEO HDTV 10BIT 40LFCSP
產(chǎn)品變化通告: ADV734x, ADV739x Feature Improvement
設(shè)計(jì)資源: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: 機(jī)頂盒,視頻播放器,顯示器
電壓 - 電源,模擬: 2.6 V ~ 3.46 V
電壓 - 電源,數(shù)字: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 786 (CN2011-ZH PDF)
配用: ADV7393-DBRDZ-ND - BOARD EVAL FOR ADV7393
EVAL-ADV7393EBZ-ND - BOARD EVAL FOR ADV7393 ENCODER
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 11 of 108
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter
Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE
Resolution
10
Bits
Integral Nonlinearity (INL)1
RSET = 510 Ω, RL = 37.5 Ω
0.5
LSBs
Differential Nonlinearity (DNL)1, 2
RSET = 510 Ω, RL = 37.5 Ω
0.5
LSBs
STANDARD DEFINTION (SD) MODE
Luminance Nonlinearity
0.5
±%
Differential Gain
NTSC
0.5
%
Differential Phase
NTSC
0.6
Degrees
Signal-to-Noise Ratio (SNR)3
Luma ramp
58
dB
Flat field full bandwidth
75
dB
ENHANCED DEFINITION (ED) MODE
Luma Bandwidth
12.5
MHz
Chroma Bandwidth
5.8
MHz
HIGH DEFINITION (HD) MODE
Luma Bandwidth
30.0
MHz
Chroma Bandwidth
13.75
MHz
1
Measured on DAC 1, DAC 2, and DAC 3.
2
Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For ve DNL, the actual step value lies below the ideal step value.
3
Measured on the ADV7392/ADV7393 operating in 10-bit input mode.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 12.
Parameter
Conditions
Min
Typ
Max
Unit
NORMAL POWER MODE1, 2
IDD3
SD (16× oversampling enabled), CVBS (only one DAC turned on)
33
mA
SD (16× oversampling enabled), YPrPb (three DACs turned on)
68
mA
ED (8× oversampling enabled)4
59
mA
HD (4× oversampling enabled)4
81
101
mA
IDD_IO
1
10
mA
One DAC enabled
50
mA
All DACs enabled
122
151
mA
IPLL
4
10
mA
SLEEP MODE
IDD
5
A
IAA
0.3
A
IDD_IO
0.2
A
IPLL
0.1
A
1
RSET = 510 Ω (all DACs operating in full-drive mode).
2
75% color bar test pattern applied to pixel data pins.
3
IDD is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5
IAA is the total current required to supply all DACs.
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