參數(shù)資料
型號(hào): ADV7195
廠商: Analog Devices, Inc.
英文描述: Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
中文描述: 多格式逐行掃描/高清晰度電視編碼器三種11位DAC和10位數(shù)據(jù)輸入
文件頁(yè)數(shù): 12/36頁(yè)
文件大?。?/td> 499K
代理商: ADV7195
REV. 0
ADV7195
–12–
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7195 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses
plus the R/
W
bit. It interprets the first byte as the device address
and the second byte as the starting subaddress. The subaddresses
autoincrement, allowing data to be written to or read from the
starting subaddress. A data transfer is always terminated by a
Stop condition. The user can also access any unique subaddress
register on a one-by-one basis without having to update all the
registers.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period the
user should issue only one Start condition, one Stop condition
or a single Stop condition followed by a single Start condition. If
an invalid subaddress is issued by the user, the ADV7195 will
not issue an acknowledge and will return to the idle condition. If
in autoincrement mode, the user exceeds the highest subaddress,
the following action will be taken:
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDA line is not pulled
low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7195 and the part will return to the idle
condition.
8
9
1 7
8
9
1 7
8
9
P
S
START ADDR R/
W
ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
1 7
Figure 12. Bus Data Transfer
Figure 12 illustrates an example of data transfer for a read sequence
and the Start and Stop conditions.
Figure 13 shows bus write and read sequences.
DATA
A(S)
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
A
(S) P
S
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
A
(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A
(S) = NO ACKNOWLEDGE BY SLAVE
A
(M) = NO ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
Figure 13. Write and Read Sequence
相關(guān)PDF資料
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ADV7195KST Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
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