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參數(shù)資料
| 型號(hào)： | ADV7183 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | Video Decoder with 9-Bit ADC(帶9位A/D轉(zhuǎn)換器和自適應(yīng)梳狀濾波器視頻譯碼器) |
| 中文描述： | 視頻解碼器（帶8位9位ADC的A / D轉(zhuǎn)換器和自適應(yīng)梳狀濾波器視頻譯碼器） |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | ADV7183 |
3
June 98 REV. 00
Preliminary Information
ADV7183
PRELMNARY
O
Vertical reference output signal or inverse composite blanking signal depending on
configuration
PIN DESCRIPTION
Mnemonic
Input/Output
Function
P15-P0
O
8-Bit Multiplexed YCrCb Pixel Port (P7-P0), 16-Bit YCrCb Pixel Port (P15-
P0), 10-Bit Multiplexed Extended YCbCr Pixel Port (P9-P0) and 20-Bit YCbCr Pixel
Port (P19-P0), P0 represents the LSB.
XTAL
I
Input terminal for 27MHz crystal oscillator or connection for external oscillator with
CMOS compatible square wave clock signal
XTAL1
0
Second terminal for crystal oscillator; not connected if external clock source is used
DVSS1-4
G
Ground for Digital supply
DVDD1-4
P
Digital Supply Voltage (5.0V)
AVSS
G
Ground for Analog Supply
AVDD
Analog Supply Voltage (5.0V)
AVDD1-3
Analog Input Channel supply Voltage (5.0)
AVSS1-4
G
Analog Input Channels ground
PVSS
G
PLL Supply Ground
PVDD
PLL Supply Voltage (5.0)
AIN1-4
I
Video Analog Input Channels
SCLOCK
I
MPU Port Serial Interface Clock Input.
SDATA
I/O
MPU Port Serial Data Input/Output.
ALSB
I
TTL Address Input. This signal set up the LSB of the MPU address.
RD
I
Read signal, read data from FIFO
DV
O
Data Valid signal, indicates data on pixel port is a valid sample
OE
I
Output Enable, enables pixel port outputs or else tri-states them
HREF
O
Horizontal reference output signal (enable via I2C); this signal is used to indicate data
on the YUV output. The positive slope indicates the begining of a new active line,
HREF is always 720 Y samples long
VREF
LLCREF
O
Clock reference ouput; this is a clock qualifier distributed by the internal CGC for a
data rate of LLC2
LLC1/PCLK
O
Dual function pin, Line locked clock system output clock (27MHz) or a FIFO output clcok ranging
from 20-35MHZ
LLC2
O
Line locked clock system output clock/2 (13.5MHz)
HLOCK
O
Horizontal locked: output signal indicating horizontal locking status
RESET
I/O
System Reset, can be configured as an Input or Output signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7183A | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7183ABST | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| ADV7183AKST | 制造商:Analog Devices 功能描述:MULTIFORMAT SDTV VIDEO DECODER 制造商:Rochester Electronics LLC 功能描述:10BIT NTSC/PAL/SECAMVIDDECOD I.C - Tape and Reel 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7183AKST-U1 | 制造商:Analog Devices 功能描述:VID DECODER 80LQFP - Bulk |
| ADV7183AKST-X2 | 制造商:Analog Devices 功能描述:VID DECODER - Bulk |
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