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參數(shù)資料
| 型號(hào)： | ADV7181DWBCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER SD/HD 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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ADV7181D
Data Sheet
Rev. A | Page 6 of 24
ANALOG SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = 40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. The recommended analog
input video signal range is 0.5 V to 1.6 V, typically 1 V p-p.
Table 3.
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
0.1
F
Input Impedance
All Pins Except for Pin 32 (FB)
Clamps switched off
10
M
Pin 32 (FB)
20
k
Common-Mode Level (CML)
1.86
V
ADC Full-Scale Level
CML + 0.8
V
ADC Zero-Scale Level
CML 0.8
V
ADC Dynamic Range
1.6
V
Clamp Level (When Locked)
CVBS input
CML 0.292
V
SCART RGB input (R, G, B signals)
CML 0.4
V
S-Video input (Y signal)
CML 0.292
V
S-Video input (C signal)
CML
V
Component input (Y, Pr, Pb signals)
CML 0.3
V
PC RGB input (R, G, B signals)
CML 0.3
V
Large Clamp Source Current
SDP only
0.75
mA
Large Clamp Sink Current
SDP only
0.9
mA
Fine Clamp Source Current
SDP only
17
A
Fine Clamp Sink Current
SDP only
17
A
1 Guaranteed by characterization.
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