參數(shù)資料
型號(hào)： ADV7181DBCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 9/24頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER SD/HD 64LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： *
Data Sheet
ADV7181D
Rev. A | Page 17 of 24
The analog input muxes of the ADV7181D must be controlled
directly. This is referred to as manual input muxing. The manual
muxing is activated by setting the ADC_SW_MAN_EN bit (see
Table 9). It affects only the analog switches in front of the ADCs.
The INSEL, SDM_SEL, PRIM_MODE, and VID_STD bits must
still be set so that the follow-on blocks process the video data in
the correct format.
Not every input pin can be routed to any ADC. The analog
signal routing inside the IC imposes restrictions on the channel
routing. See Table 9 for an overview of the routing capabilities
inside the chip. The four mux sections can be controlled by the
reserved control signal buses ADC0_SW[3:0], ADC1_SW[3:0],
ADC2_SW[3:0], and ADC3_SW[3:0].
Table 9 explains the ADC mapping configuration for the following:
ADC_SW_MAN_EN, manual input muxing enable,
IO map, Address C4[7]
ADC0_SW[3:0], ADC0 mux configuration, IO map,
Address C3[3:0]
ADC1_SW[3:0], ADC1 mux configuration, IO map,
Address C3[7:4]
ADC2_SW[3:0], ADC2 mux configuration, IO map,
Address C4[3:0]
ADC3_SW[3:0], ADC3 mux configuration, IO map,
Address F3[7:4]
Table 9. Manual MUX Settings for All ADCs
ADC_SW_MAN_EN = 1
ADC0_SW[3:0]
ADC0
Connection
ADC1_SW[3:0]
ADC1
Connection
ADC2_SW[3:0]
ADC2
Connection
ADC3_SW[3:0]
ADC3
Connection
0000
N/A
0000
N/A
0000
N/A
0000
N/A
0001
A
IN2
0001
N/A
0001
N/A
0001
N/A
0010
A
IN3
0010
N/A
0010
A
IN3
0010
N/A
0011
A
IN5
0011
A
IN5
0011
N/A
0011
N/A
0100
A
IN6
0100
A
IN6
0100
A
IN6
0100
A
IN6
0101
A
IN8
0101
A
IN8
0101
A
IN8
0101
N/A
0110
A
IN10
0110
A
IN10
0110
A
IN10
0110
N/A
0111
N/A
0111
N/A
0111
N/A
0111
N/A
1000
N/A
1000
N/A
1000
N/A
1000
N/A
1001
A
IN1
1001
N/A
1001
N/A
1001
A
IN1
1010
N/A
1010
N/A
1010
N/A
1010
N/A
1011
A
IN4
1011
A
IN4
1011
N/A
1011
N/A
1100
N/A
1100
N/A
1100
N/A
1100
N/A
1101
A
IN7
1101
A
IN7
1101
A
IN7
1101
N/A
1110
A
IN9
1110
A
IN9
1110
A
IN9
1110
N/A
1111
N/A
1111
N/A
1111
N/A
1111
N/A
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