參數(shù)資料
型號(hào): ADV7179BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 36/52頁(yè)
文件大小: 0K
描述: IC ENCODER VID NTSC/PAL 40LFCSP
產(chǎn)品培訓(xùn)模塊: Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: 數(shù)碼相機(jī),手機(jī),便攜式視頻
電壓 - 電源,模擬: 2.8 V,3.3 V
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 786 (CN2011-ZH PDF)
ADV7174/ADV7179
Rev. B | Page 41 of 52
APPENDIX 2—CLOSED CAPTIONING
The ADV7174/ADV7179 supports closed captioning, conform-
ing to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency-locked and phase-locked to the caption data. After
the clock run-in signal, the blanking level is held for 2 data bits
and is followed by a Logic 1 start bit. 16 bits of data follow the
start bit. These consist of two 8-bit bytes, 7 data bits, and 1 odd
parity bit. The data for these bytes is stored in closed captioning
Data Registers 0 and 1.
The ADV7174/ADV7179 also supports the extended closed
captioning operation, which is active during even fields, and is
encoded on scan Line 284. The data for this operation is stored
in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are automatically generated by the
ADV7174/ADV7179. All pixel inputs are ignored during Lines
21 and 284. FCC Code of Federal Regulations (CFR) 47 Section
15.119 and EIA-608 describe the closed captioning information
for Lines 21 and 284.
The ADV7174/ADV7179 uses a single buffering method. This
means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed
captioning data unlike other 2-byte deep buffering systems. The
data must be loaded at least one line before (Line 20 or Line 283)
it is outputted on Line 21 and Line 284. A typical implementation
of this method is to use VSYNC to interrupt a microprocessor,
which in turn loads the new data (two bytes) every field. If no
new data is required for transmission, you must insert zeros in
both the data registers; this is called nulling. It is also important
to load control codes, all of which are double bytes, on Line 21,
or a TV cannot recognize them. If you have a message such as
“Hello World,” which has an odd number of characters, it is
important to pad it out to an even number to get the end of the
caption 2-byte control code to land in the same field.
50 IRE
12.91
μs
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
D0–D6
10.003
μs
33.764
μs
40 IRE
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
7 CYCLES
OF 0.5035 MHz
(CLOCK RUN-IN)
10.5 ± 0.25
μs
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
27.382
μs
BYTE 0
BYTE 1
02980-A
-055
Figure 56. Closed Captioning Waveform (NTSC)
相關(guān)PDF資料
PDF描述
VE-231-IY-F3 CONVERTER MOD DC/DC 12V 50W
VE-B7L-IW-B1 CONVERTER MOD DC/DC 28V 100W
CS4954-CQZ IC VIDEO ENCODER NTSC/PAL 48TQFP
VE-230-IY-F4 CONVERTER MOD DC/DC 5V 50W
VE-B7K-IX-B1 CONVERTER MOD DC/DC 40V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7179BCPZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
ADV7179BCPZ-REEL 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP T/R
ADV7179BCPZ-REEL2 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
ADV7179KCP 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:CHIP SCALE NTSC/PAL VID ENCODER APM I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7179KCP1 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management