參數(shù)資料
型號(hào)： ADV7177KSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/44頁(yè)
文件大小： 0K
描述： IC DAC VIDEO NTSC 3-CH 44MQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，電視
電壓 - 電源，模擬： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7177/ADV7178
Rev. C | Page 17 of 44
VIDEO TIMING DESCRIPTION
The ADV7177/ADV7178 are intended to interface to off-the-
shelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7177/ADV7178 accept 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port, and have several video timing modes
allowing them to be configured as either a system master
video timing generator or a slave to the system video timing
generator. The ADV7177/ADV7178 generate all of the required
horizontal and vertical timing periods and levels for the analog
video outputs. It is important to note that the CCIR-656 data
stream should not contain ancillary data packets as per the
BT1364 specification. This data can corrupt the internal
synchronization circuitry of the devices, resulting in loss of
synchronization on the output.
The ADV7177/ADV7178 calculate the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration
and equalization pulses are inserted where required.
In addition, the ADV7177/ADV7178 support a PAL or NTSC
square pixel operation in slave mode. The parts require an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct
location for the new clock frequencies.
The ADV7177/ADV7178 have four distinct master and four
distinct slave timing configurations. Timing control is
established with the bidirectional SYNC, BLANK, and
FIELD/VSYNC pins. Timing Mode Register 1 can also be used
to vary the timing pulse widths and where they occur in
relation to each other.
Vertical Blanking Data Insertion (VBI)
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre- and post-
equalization pulses (see the Typical Performance Characteristics
section). This mode of operation is called partial blanking and
is selected by setting MR31 to 1. It allows the insertion of any
VBI data (opened VBI) into the encoded output waveform. This
data is present in the digitized incoming YCbCr data stream
(for example, WSS data, CGMS, and VPS). Alternatively, the
entire VBI can be blanked (no VBI data inserted) on these lines
by setting MR31 to 0.
Table 10. Luminance Internal Filter Specifications
Filter Selection
MR04
MR03
Pass-Band
Cutoff (MHz)
Pass-Band
Ripple (dB)
Stop-Band
Cutoff (MHz)
Stop-Band
Attenuation (dB)
F3 dB
NTSC
0
2.3
0.026
7.0
>54
4.2
PAL
0
3.4
0.098
7.3
>50
5.0
NTSC
0
1
1.0
0.085
3.57
>27.6
2.1
PAL
0
1
1.4
0.107
4.43
>29.3
2.7
NTSC/PAL
1
0
4.0
0.150
7.5
>40
5.35
NTSC
1
2.3
0.054
7.0
>54
4.2
PAL
1
3.4
0.106
7.3
>50.3
5.0
Table 11. Chrominance Internal Filter Specifications
Filter Selection
Pass-Band
Cutoff (MHz)
Pass-Band
Ripple (dB)
Stop-Band
Cutoff (MHz)
Stop-Band
Attenuation (dB)
Attenuation
@ 1.3 MHz (dB)
F3 dB
NTSC
1.0
0.085
3.2
>40
0.3
2.05
PAL
1.3
0.04
4.0
>40
0.02
2.45
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