參數(shù)資料
型號(hào): ADV7176A
廠商: Analog Devices, Inc.
英文描述: High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 高品質(zhì),10位,數(shù)字無(wú)線電咨詢委員會(huì),601到PAL / NTSC制式視頻編碼器
文件頁(yè)數(shù): 19/52頁(yè)
文件大小: 629K
代理商: ADV7176A
ADV7175A/ADV7176A
–19–
REV. B
622
623
624
625
1
2
3
4
5
6
7
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
DISPLAY
320
VSYNC
Figure 22. Timing Mode 2 (PAL)
Mode 2: Master Option
HSYNC
,
VSYNC
,
BLANK
(T iming Register 0 T R0 = X X X X X 1 0 1)
In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an Odd Field. A
VSYNC
low transition when
HSYNC
is high indicates the start
of an even field. T he
BLANK
signal is optional. When the
BLANK
input is disabled, the ADV7175A/ADV7176A automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NT SC) and Figure 22 (PAL ). Figure 23
illustrates the
HSYNC
,
BLANK
and
VSYNC
for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC
,
BLANK
and
VSYNC
for an odd-to-even field transition relative to the pixel data.
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
HSYNC
VSYNC
BLANK
PIXEL
DATA
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Cb
Y
Cr
Y
Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
HSYNC
VSYNC
BLANK
PIXEL
DATA
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
Cb
Y
Cr
Y
Cb
Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
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