參數(shù)資料
型號(hào): ADV7176
廠商: Analog Devices, Inc.
英文描述: Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
中文描述: 綜合數(shù)字無(wú)線(xiàn)電咨詢(xún)委員會(huì),601 YCrCb到PAL / NTSC制式視頻編碼器
文件頁(yè)數(shù): 8/36頁(yè)
文件大?。?/td> 447K
代理商: ADV7176
ADV7175/ADV7176
REV. A
–8–
COLOR BAR GE NE RAT ION
T he ADV7175/ADV7176 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NT SC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
T hese are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
SQUARE PIX E L MODE
T he ADV7175/ADV7176 can be used to operate in square
pixel mode. For NT SC operation an input clock of 24.54 MHz
is required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. T he internal filters scale accordingly for
square pixel mode operation.
COLOR SIGNAL CONT ROL
T he color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONT ROL
T he burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NT SC PE DE ST AL CONT ROL
T he pedestal information on both odd and even fields can be
controlled on a line by line basis using the NT SC Pedestal
Control Registers. T his allows the pedestals to be controlled
during the vertical blanking interval (Lines 10 to 25).
SUBCARRIE R RE SE T
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used in subcarrier reset mode. T he subcarrier will reset to field
0 at the start of the following field when a high to low transition
occurs on this input pin.
RE AL T IME CONT ROL
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used to lock an external video source. T he real time control
mode allows the ADV7175/ADV7176 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs out a digi-
tal datastream in the RT C format (such as a Phillips SAA7110
video decoder), the part will automatically change to the com-
pensated subcarrier frequency on a line by line basis. T his
digital datastream is 67 bits wide and the subcarrier is con-
tained in bits 0 to 21. Each bit is 2 clock cycles long.
COMPOSITE
VIDEO
e.g. VCR
OR CABLE
M
U
X
HSYNC
FIELD/
VSYNC
ADV7175/ADV7176
CLOCK
GREEN/LUMA/Y
RED/CHROMA/V
BLUE/COMPOSITE/U
COMPOSITE
P7–P0
SCRESET/RTC
MPEG
DECODER
VIDEO
DECODER
(e.g.SAA7110)
Figure 12. RTC Connections
PIX E L T IMING DE SCRIPT ION
T he ADV7175/ADV7176 can operate in either 8-bit or 16-bit
YCrCb Mode.
8-Bit Y CrCb Mode
T his default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. T he inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. T he Y, Cb and Cr data are input on
a rising clock edge.
16-Bit Y CrCb Mode
T his mode accepts Y inputs through the P7-P0 pixel inputs and
multiplexed CrCb inputs through the P15-P8 pixel inputs. T he
data is loaded on every second rising clock edge of CLOCK .
T he inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
VIDE O T IMING DE SCRIPT ION
T he ADV7175/ADV7176 is intended to interface to off the shelf
MPEG1 and MPEG2 Decoders. As a consequence the
ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing gen-
erator. T he ADV7175/ADV7176 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
T he ADV7175/ADV7176 calculates the width and placement
of analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.
FREQUENCY – MHz
0
2
4
6
8
12
10
A
–10
–40
–20
0
–80
–60
–100
–50
–30
–90
–70
Figure 10. NTSC UV Filter
FREQUENCY – MHz
0
2
4
6
8
12
10
A
–10
–40
–20
0
–80
–60
–100
–50
–30
–90
–70
Figure 11. PAL UV Filter
(Continued on page 15)
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