參數(shù)資料
型號(hào)： ADV7175A
廠商： Analog Devices, Inc.
英文描述： High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述： 高品質(zhì)，10位，數(shù)字無(wú)線電咨詢(xún)委員會(huì)，601到PAL / NTSC制式視頻編碼器
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 629K
代理商： ADV7175A
ADV7175A/ADV7176A
–26–
REV. B
Genlock Control (MR22–MR21)
T hese bits control the genlock feature of the ADV7175A/
AD V7176A. Setting MR21 to a L ogic “1” configures the
SCRESET /RT C pin as an input. Setting MR22 to Logic Level
“0” configures the SCRESET /RT C pin as a subcarrier reset
input, therefore, the subcarrier will reset to Field 0, following a
high-to-low transition on the SCRESET /RT C pin. Setting
MR22 to Logic Level “1” configures the SCRESET /RT C pin as
a real-time control input.
Active Video Line Control (MR23)
T his bit switches between two active video line durations. A
zero selects IT U-R BT .470 (720 pixels PAL/NT SC) and a one
selects IT U-R/SMPT E “analog” standard for active video dura-
tion (710 pixels NT SC 702 pixels PAL).
Chrominance Control (MR24)
T his bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
T his bit enables the burst information to be switched on and off
the video output.
RGB/Y UV Control (MR26)
T his bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Lower Power Control (MR27)
T his bit enables the lower power mode of the ADV7175A/
ADV7176A. T his will reduce the DAC current by 50%.
NT SC PE DE ST AL/PAL T E LE T E X T CONT ROL
RE GIST E RS 3–0 (PCE 15–0, PCO15–0)/ (T X E 15–0, T X O15–0)
(Subaddress [SR4–SR0] = 11–0E H)
T hese 8-bit wide registers are used to set up the NT SC pedes-
tal/PAL teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 40 and 41 show
the four control registers. A Logic “1” in any of the bits of these
registers has the effect of turning the pedestal OFF on the
equivalent line when used in NT SC. A Logic “1” in any of the
bits of these registers has the effect of turning teletext ON the
equivalent line when used in PAL.
FIELD 1/3
PCO6
PCO5
PCO3
PCO1
PCO4
PCO2
PCO0
PCO7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO14
PCO13
PCO11
PCO9
PCO12
PCO10
PCO8
PCO15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
FIELD 2/4
PCE6
PCE5
PCE3
PCE1
PCE4
PCE2
PCE0
PCE7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE14
PCE13
PCE11
PCE9
PCE12
PCE10
PCE8
PCE15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
Figure 40. Pedestal Control Registers
FIELD 1/3
FIELD 1/3
FIELD 2/4
FIELD 2/4
TXO6
TXO5
TXO3
TXO1
TXO4
TXO2
TXO0
TXO7
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8 LINE 7
TXO14
TXO13
TXO11
TXO9
TXO12
TXO10
TXO8
TXO15
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXE6
TXE5
TXE3
TXE1
TXE4
TXE2
TXE0
TXE7
TXE14
TXE13
TXE11
TXE9
TXE12
TXE10
TXE8
TXE15
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8
LINE 7
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
Figure 41. Teletext Control Registers
MODE RE GIST E R 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
Mode Register 3 is an 8-bit wide register.
Figure 42 shows the various operations under the control of
Mode Register 3.
MR3 BIT DE SCRIPT ION
Revision Code (MR30)
T his bit is read only and indicates the revision of the device.
VBI Pass-T hrough Control (MR31)
T his bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Reserved (MR33–MR32)
T hese bits are reserved.
T eletext E nable (MR34)
T his bit must be set to “1” to enable teletext data insertion on
the T T X pin.
MR21
MR27
MR22
MR23
MR26
MR25
MR24
MR20
CHROMINANCE
CONTROL
MR24
0
1
ENABLE COLOR
DISABLE COLOR
GENLOCK SELECTION
x
0
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
1
1
MR22 MR21
RGB/YUV
CONTROL
MR26
0
1
RGB OUTPUT
YUV OUTPUT
SQUARE PIXEL
CONTROL
MR20
0
1
DISABLE
ENABLE
BURST
CONTROL
0
1
ENABLE BURST
DISABLE BURST
MR25
LOWER POWER
MODE
MR27
0
1
DISABLE
ENABLE
ACTIVE VIDEO LINE WIDTH
CONTROL
MR23
0
1
720 PIXELS ACTIVE LINE
ITU-R/SMPTE ACTIVE LINE
Figure 39. Mode Register 2
相關(guān)PDF資料
PDF描述
ADV7175AKS High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7176A High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7176AKS High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7176A* High Quality. 10-Bit. Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7175 Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7175AKS 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7175KS 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176A 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
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