參數(shù)資料
型號: ADV7175
廠商: Analog Devices, Inc.
英文描述: Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
中文描述: 綜合數(shù)字無線電咨詢委員會,601 YCrCb到PAL / NTSC制式視頻編碼器
文件頁數(shù): 9/36頁
文件大?。?/td> 447K
代理商: ADV7175
ADV7175/ADV7176
REV. A
–9–
Mode 0 (CCIR-656): Slave Option.
(T iming Register 0 T R0 = X X X X X 0 0 0)
T he ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. T he
HSYNC
, FIELD/
VSYNC
and
BLANK
(if not used) pins should be tied high in this mode.
C
r
C
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
YC
r
C
b
YC
r
C
b
YC
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 PIXELS
4 PIXELS
268 PIXELS
1440 PIXELS
4 PIXELS
4 PIXELS
280 PIXELS
1440 PIXELS
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC SYSTEM
PAL SYSTEM
Figure 13. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option.
(T iming Register 0 T R0 = X X X X X 0 0 1)
T he ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. T he H bit is output on the
HSYNC
pin, the V bit is output on the
BLANK
pin and the F bit is
output on the FIELD/
VSYNC
pin. Mode 0 is illustrated in Figure 14 (NT SC) and Figure 15 (PAL). T he H, V and F transitions
relative to the video waveform are illustrated in Figure 16.
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
H
V
F
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
H
V
F
Figure 14. Timing Mode 0 (NTSC Master Mode)
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