VAA = 4.75 V to 5.25 V1, VR" />
參數(shù)資料
型號(hào): ADV7171KSZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 62/64頁(yè)
文件大?。?/td> 0K
描述: IC DAC VIDEO ENC NTSC 44-MQFP
產(chǎn)品培訓(xùn)模塊: Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: 機(jī)頂盒,視頻播放器
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應(yīng)商設(shè)備封裝: 44-MQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 786 (CN2011-ZH PDF)
ADV7170/ADV7171
Rev. C | Page 7 of 64
TIMING SPECIFICATIONS
VAA = 4.75 V to 5.25 V1, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
MPU PORT3, 4
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulse Width, t1
0.6
μs
SCLOCK Low Pulse Width, t2
1.3
μs
Hold Time (Start Condition), t3
After this period the first clock is generated
Relevant for repeated start condition
0.6
μs
Setup Time (Start Condition), t4
0.6
μs
Data Setup Time, t5
100
ns
SDATA, SCLOCK Rise Time, t6
300
ns
SDATA, SCLOCK Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
0.6
μs
ANALOG OUTPUTS3, 5
Analog Output Delay
7
ns
DAC Analog Output Skew
0
ns
CLOCK CONTROL AND PIXEL PORT5, 6
fCLOCK
27
MHz
Clock High Time, t9
8
ns
Clock Low Time, t10
8
ns
Data Setup Time, t11
3.5
ns
Data Hold Time, t12
4
ns
Control Setup Time, t11
4
ns
Control Hold Time, t12
3
ns
Digital Output Access Time, t13
11
16
ns
Digital Output Hold Time, t144
8
ns
Pipeline Delay, t154
48
Clock cycles
Digital Output Access Time, t16
20
ns
Data Setup Time, t17
2
ns
Data Hold Time, t18
6
ns
RESET CONTROL3, 4
RESET Low Time
6
ns
1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V range.
2 Ambient temperature range TMIN to TMAX: 40°C to +85°C. The die temperature, TJ, must always be kept below 110°C.
3 TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
4 Guaranteed by characterization
5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6 Pixel port consists of the following:
Pixel inputs:
P15–P0
Pixel controls:
HSYNC, FIELD/VSYNC, BLANK
Clock input:
CLOCK
7 Teletext port consists of the following:
Teletext output: TTXREQ
Teletext input:
TTX
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