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參數(shù)資料
| 型號： | ADV7150LS85 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQFP160 |
| 封裝： | POWER, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 447K |
| 代理商： | ADV7150LS85 |
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ADV7150
–10–
REV. A
PIN FUNCT ION DE SCRIPT ION
Mnemonic
Function
RED (R0
A
. . . R0
D
–R7
A
. . . R7
D
),
GREEN (G0
A
. . . G0
D
–G7
A
. . . G7
D
),
BLUE (B0
A
. . . B0
D
–B7
A
. . . B7
D
)
Pixel Port (T T L Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, 8
bits for Green and 8 bits for Blue. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. It can
be configured for 24-Bit T rue-Color Data, 8-Bit Pseudo-Color Data and 15-Bit T rue-Color
Data formats. Pixel Data is latched into the device on the rising edge of LOADIN.
Palette Priority Selects (T T L Compatible Inputs): T hese pixel port select inputs deter-
mine whether or not the device’s pixel data port is selected on a pixel by pixel basis.
T he palette selects allow switching between multiple palette devices. T he device can be
preprogrammed to completely shut off the DAC analog outputs. If the values of PS0
and PS1 match the values programmed into bits MR16 and MR17 of the Mode Regis-
ter, then the device is selected. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. PS0 and
PS1 are latched into the device on the rising edge of LOADIN.
Pixel Data Load Input (T T L Compatible Input). T his input latches the multiplexed
pixel data, including PS0–PS1,
BLANK
and
SYNC
into the device.
Pixel Data Load Output (T T L Compatible Output). T his output control signal runs at
a divided down frequency of the pixel CLOCK input. Its frequency is a function of the
multiplex rate. It can be used to directly or indirectly drive LOADIN
f
LOADOUT
= f
CLOCK
/M
where
M
= 1 for 1:1 Multiplex Mode
where
M
= 2 for 2:1 Multiplex Mode
where
M
= 4 for 4:1 Multiplex Mode.
Programmable Clock Output (T T L Compatible Output). T his output control signal
runs at a divided down frequency of the pixel CLOCK input. Its frequency is user
programmable and is determined by bits CR30 and CR31 of Command Register 3
f
PRGCKOUT
= f
CLOCK
/N
where
N
= 4, 8, 16 and 32.
Video Shift Clock Input (T T L Compatible Input). T he signal on this input is internally
gated synchronously with the
BLANK
signal. T he resultant output, SCK OUT , is a
video clocking signal that is stopped during video blanking periods.
Video Shift Clock Output (T T L Compatible Output). T his output is a synchronously
gated version of SCK IN and
BLANK
. SCK OUT , is a video clocking signal that is
stopped during video blanking periods.
Clock Inputs (ECL Compatible Inputs). T hese differential clock inputs are designed to
be driven by ECL logic levels configured for single supply (+5 V) operation. T he clock
rate is normally the pixel clock rate of the system.
Composite Blank (T T L Compatible Input). T his video control signal drives the analog
outputs to the blanking level.
Composite-Sync Input (T T L Compatible Input). T his video control signal drives the
IOG analog output to the
SYNC
level. It is only asserted during the blanking period.
CR22 in Command Register 2 must be set if
SYNC
is to be decoded onto the analog
output, otherwise the
SYNC
input is ignored.
Composite-Sync Output (T T L Compatible Output). T his video output is a delayed
version of
SYNC
. T he delay corresponds to the number of pipeline stages of the device.
Databus (T T L Compatible Input/Output Bus). Data, including color palette values and
device control information is written to and read from the device over this 10-bit, bidi-
rectional databus. 10-bit data or 8-bit data can be used. T he databus can be configured
for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any un-
used bits of the databus should be terminated through a resistor to either the digital
power plane (V
CC
) or GND.
Chip Enable (T T L Compatible Input). T his input must be at Logic “0,” when writing
to or reading from the device over the databus (D0–D9). Internally, data is latched on
the rising edge of
CE
.
PS0
A
. . . PS0
D
, PS1
A
. . . PS1
D
LOADIN
LOADOUT
PRGCK OUT
SCK IN
SCK OUT
CLOCK ,
CLOCK
BLANK
SYNC
SYNCOUT
D0–D9
CE
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