參數(shù)資料
型號: ADV7123KSTZ140
廠商: Analog Devices Inc
文件頁數(shù): 13/24頁
文件大?。?/td> 0K
描述: IC DAC VIDEO TRPL HI SPD 48-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
電壓電源: 單電源
功率耗散(最大): 30mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
輸出數(shù)目和類型: 6 電流,單極
采樣率(每秒): 140M
產(chǎn)品目錄頁面: 786 (CN2011-ZH PDF)
ADV7123
Rev. D | Page 20 of 24
ANALOG SIGNAL INTERCONNECT
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
should be as close as possible to the ADV7123 to minimize
reflections.
Place the ADV7123 as close as possible to the output connec-
tors, thus minimizing noise pickup and reflections due to
impedance mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high
frequency power supply rejection.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI, which is available from
Analog Devices at www.analog.com.
35
36
37
33
31
27
R9 TO R0
39 TO 48
COMP
VAA
VREF
RSET
IOR
75
75
75
COAXIAL CABLE
75
POWER SUPPLY DECOUPLING
(0.1F AND 0.01F CAPACITOR
FOR EACH VAA GROUP)
AD1580
ADV7123
MONITOR (CRT)
1
2
BNC
CONNECTORS
COMPLEMENTARY
OUTPUTS
75
1k
RSET
530
IOG
IOB
12 SYNC
11
BLANK
24 CLOCK
38 PSAVE
GND
25, 26
13, 29,
30
VIDEO
DATA
INPUTS
G9 TO G0
1TO 10
B9 TO B0
14 TO 23
IOR
IOG
IOB
75
75
32
28
34
0.1F
1F
0.01F
00
21
5-
0
28
Figure 28. Typical Connection Diagram
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