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參數(shù)資料
| 型號： | ADV7120KPZ80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO 3CH 80MHZ 44PLCC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1 |
| 設(shè)置時間： | 12ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 625mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 3 電流，單極 |
| 采樣率（每秒）： | 80M |
REV. B
–2–
ADV7120–SPECIFICATIONS
Parameter
All Versions
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC)
8
Bits
Accuracy (Each DAC)
Integral Nonlinearity, INL
± 1
LSB max
Differential Nonlinearity, DNL
±0.5
LSB max
Guaranteed Monotonic
Gray Scale Error
± 5
% Gray Scale max
Max Gray Scale Current: IOG = (VREF* 12,082/RSET) mA
IOR, IOB = (VREF* 8,627/RSET) mA
Coding
Binary
DIGITAL INPUTS
Input High Voltage, VINH
2
V min
Input Low Voltage, VINL
0.8
V max
Input Current, IIN
± 1
A max
VIN = 0.4 V or 2.4 V
Input Capacitance, CIN
2
10
pF max
ANALOG OUTPUTS
Gray Scale Current Range
15
mA min
22
mA max
Output Current
White Level Relative to Blank
17.69
mA min
Typically 19.05 mA
20.40
mA max
White Level Relative to Black
16.74
mA min
Typically 17.62 mA
18.50
mA max
Black Level Relative to Blank
0.95
mA min
Typically 1.44 mA
1.90
mA max
Blank Level on IOR, IOB
0
A min
Typically 5
A
50
A max
Blank Level on IOG
6.29
mA min
Typically 7.62 mA
9.5
mA max
Sync Level on IOG
0
A min
Typically 5
A
50
A max
LSB Size
69.1
A typ
DAC to DAC Matching
5
% max
Typically 2%
Output Compliance, VOC
–1
V min
+1.4
V max
Output Impedance, ROUT
2
100
k
typ
Output Capacitance, COUT
2
30
pF max
IOUT = 0 mA
VOLTAGE REFERENCE
Voltage Reference Range, VREF
1.14/1.26
V min/V max
VREF = 1.235 V for Specified Performance
Input Current, IVREF
–5
mA typ
POWER REQUIREMENTS
VAA
5
V nom
IAA
125
mA max
Typically 80 mA: 80 MHz Parts
100
mA max
Typically 70 mA: 50 MHz & 35 MHz Parts
Power Supply Rejection Ratio
0.5
%/% max
Typically 0.12%/%: f = 1 kHz, COMP = 0.1
F
Power Dissipation
625
mW max
Typically 400 mW: 80 MHz Parts
500
mW max
Typically 350 mW: 50 MHz & 30 MHz Parts
DYNAMIC PERFORMANCE
Glitch Impulse
2, 3
50
pV secs typ
DAC Noise
2, 3, 4
200
pV secs typ
Analog Output Skew
2
ns max
Typically 1 ns
NOTES
1Temperature range (T
MIN to TMIN); 0°C to +70°C.
2Sample tested at +25
°C to ensure compliance.
3TTL input values are 0 to 3 volts, with input rise/fall times
≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
4This includes effects due to clock and data feedthrough as well as RGB analog crosstalk.
Specifications subject to change without notice.
(VAA = +5 V
5%; VREF = +1.235 V; RL = 37.5
, CL = 10 pF; RSET = 560
.
ISYNC connected to I0G. All Specifications TMIN to TMAX
1 unless otherwise noted.)
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