
ADV601LC
–35–
REV. 0
Multiplexed Philips Video Timing
The diagrams in this section show transfer timing for pixel (YCrCb) data in Multiplexed Philips video mode. For line (horizontal)
and frame (vertical) data transfer timing, see Figure 25. All output values assume a maximum pin loading of 50 pF. Note that in
timing diagrams for Multiplexed Philips video, the label CTRL indicates the VSYNC, HSYNC and FIELD pins.
Table XXIII. Multiplexed Philips Video—Decode and Master Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Unit
tVDATA_DMM_D
VDATA Bus, Decode Master Multiplexed Philips, Delay
N/A
14
ns
tVDATA_DMM_OH
VDATA Bus, Decode Master Multiplexed Philips, Output Hold
4
N/A
ns
tCTRL_DMM_D
CTRL Signals, Decode Master Multiplexed Philips, Delay
N/A
11
ns
tCTRL_DMM_OH
CTRL Signals, Decode Master Multiplexed Philips, Output Hold
5
N/A
ns
(O) CTRL
(O) VCLKO
t
CTRL_DMM_OH
(O) VDATA
t
VDATA_DMM_OH
t
VDATA_DMM_D
VALID
t
CTRL_DMM_D
VALID
Figure 23. Multiplexed Philips Video—Decode and Master Pixel (YCrCb) Transfer Timing
Table XXIV. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Unit
tVDATA_DSM_D
VDATA Bus, Decode Slave Multiplexed Philips, Delay
N/A
14
ns
tVDATA_DSM_OH
VDATA Bus, Decode Slave Multiplexed Philips, Output Hold
4
N/A
ns
tCTRL_DSM_S
CTRL Signals, Decode Slave Multiplexed Philips, Setup
16
N/A
ns
tCTRL_DSM_H
CTRL Signals, Decode Slave Multiplexed Philips, Hold
42
N/A
ns
(I) CTRL
(O) VCLKO
(O) VDATA
t
CTRL_DSM_H
VALID
t
VDATA_DSM_OH
VALID
t
VDATA_DSM_D
t
CTRL_DSM_S
Figure 24. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Transfer Timing