參數(shù)資料
型號: ADV476KN50
廠商: ANALOG DEVICES INC
元件分類: 顯示控制器
英文描述: Circular Connector; No. of Contacts:66; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:19-35
中文描述: PALETTE-DAC DSPL CTLR, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 9/12頁
文件大小: 175K
代理商: ADV476KN50
ADV476
REV. B
–9–
PC BOARD LAY OUT CONSIDE RAT IONS
T he ADV476 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. For optimum sys-
tem noise performance, it is imperative that great care be given
to the PC board layout. T he layout should be optimized for low-
est noise on the ADV476 power and ground lines. T his can be
achieved by shielding the digital inputs and providing good
decoupling. T he lead length between groups of V
CC
and GND
pins should by minimized so as to minimize inductive ringing.
Ground Planes
T he ground plane should encompass all ADV476 ground pins,
voltage reference circuitry, power supply bypass circuitry, the
analog output traces and all the digital signal traces leading up
to the ADV476.
Power Planes
T he PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. T he analog
power plane (V
CC
) should encompass the ADV476 and all asso-
ciated analog circuitry. T his power plane should be connected
to the regular PCB power plane at a single point through a fer-
rite bead, as illustrated in Figure 7. T his bead should be located
within three inches of the ADV476.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV476 power pins, current reference circuitry
and any output amplifiers.
T he PCB power and ground planes should not overlay portions
of the analog power plane. K eeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors, see Figure 7.
Optimum performance is achieved by the use of 0.1
μ
F ceramic
capacitors. T his should be done by placing the capacitors as
close as possible to the device with the capacitor leads as short
as possible, thus minimizing lead inductance.
It is important to note that while the ADV476 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX 002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three terminal voltage regulator.
Digital Signal Interconnect
T he digital signal lines to the ADV476 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.
Due to the high clock rates used, long clock lines to the
ADV476 should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane and not
the analog power plane.
Analog Signal Interconnect
T he ADV476 should be located as close as possible to the out-
put connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
T he video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75
. T his termi-
nation resistance should be as close as possible to the ADV476
to minimize reflections.
Note: For additional information on PC Board-Layout see
Application Note “Design and Layout of a Video Graphics
System for Reduced EMI”, available from Analog Devices
(Pub. No. E1309–15–10/89).
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