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參數(shù)資料
| 型號(hào)： | ADV3227ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SW 16X16 100LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 16:16 |
| 電壓電源： | 雙電源 |
| 電壓 - 電源，單路/雙路(±)： | ±5V |
| 電流 - 電源： | 125mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 100ピンLFCSP-VQ（12x12） |
| 包裝： | 管件 |
ADV3226/ADV3227
Rev. 0 | Page 22 of 24
data that was just shifted in. The update registers are asynchronous,
and when UPDATE is low (and CE is low), they are transparent.
If more than one ADV3226/ADV3227 device is to be serially
programmed in a system, the DATAOUT signal from one
device can be connected to the DATAIN of the next device to
form a serial chain. Connect all of the CLK, CE, UPDATE, and
SER/PAR pins in parallel and operate them as described previously
in this section. The serial data is input to the DATAIN pin of
the first device of the chain, and it ripples through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence (80 bits) is multiplied by the number
of devices in the chain.
Parallel Programming
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
Parallel programming allows the modification of a single output
at a time. Because this takes only one CLK/UPDATE cycle, signifi-
cant time savings can be realized by using parallel programming.
An important consideration in using parallel programming is
that the RESET signal does not reset all registers in the ADV3226/
ADV3227. When taken low, the RESET signal sets each output
to the disabled state. This is helpful during power-up to ensure
that two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device
generally contain random data, even though the RESET signal
was asserted. If parallel programming is used to program one
output, that output is properly programmed, but the rest of the
device has a random program state depending on the internal
register content at power-up. Therefore, when using parallel
programming, it is essential that all outputs be programmed to
a desired state after power-up to ensure that the programming
matrix is always in a known state. From this point, parallel pro-
gramming can be used to modify either a single output or multiple
outputs at one time.
Similarly, if both CE and UPDATE are taken low after initial
power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent programming
the crosspoint into an unknown state, do not apply low logic
levels to both CE and UPDATE after power is initially applied.
To eliminate the possibility of programming the matrix to an
unknown state, after initial power-up, program the full shift
register one time to a desired state using either serial or parallel
programming.
To change the programming of an output via parallel program-
ming, take the SER/PAR and UPDATE pins high, and take the
CE pin low. The CLK signal should be in the high state. Place
the 4-bit address of the output to be programmed on A0 to A3.
The first four data bits (D0 to D3) contain the information that
identifies the input that is programmed to the addressed output.
The fifth data bit (D4) determines the enabled state of the out-
put. If D4 is low (output disabled), the data on D0 to D3 does
not matter.
After the address and data signals are established, they can be
latched into the shift register by pulling the CLK signal low;
however, the matrix is not programmed until the UPDATE
signal is taken low. In this way, it is possible to latch in new data
for several or all of the outputs first via successive negative transi-
tions of CLK while UPDATE is held high and then have all the
new data take effect when UPDATE goes low. Use this technique
when programming the device for the first time after power-up
when using parallel programming. In parallel mode, the CLK
pin is level sensitive, whereas in serial mode, it is edge triggered.
POWER-ON RESET
When powering up the ADV3226/ADV3227, it is usually desirable
to have the outputs come up in the disabled state. When taken
low, the RESET pin causes all outputs to be in the disabled state.
However, the RESET signal does not reset all registers in the
ADV3226/ADV3227. This is important when operating in the
parallel programming mode. Refer to the
section for information about programming internal registers
after power-up. Serial programming programs the entire matrix
each time; therefore, no special considerations apply.
Because the data in the shift register is random after power-up,
it should not be used to program the matrix, or the matrix can
enter unknown states. To prevent the matrix from entering
unknown states, do not apply logic low signals to both CE and
UPDATE initially after power-up. Instead, first load the shift
register with the data and then take UPDATE low to program
the device.
The RESET pin has a 20 kΩ pull-up resistor to DVCC that can be
used to create a simple power-up reset circuit. A capacitor from
RESET to ground holds the RESET pin low for a period during
which the rest of the device stabilizes. The low condition causes
all of the outputs to be disabled. The capacitor then charges
through the pull-up resistor to the high state, thereby allowing full
programming capability of the device.
GAIN SELECTION
The 16 × 16 crosspoints come in two versions, depending on
the gain of the analog circuit path. The ADV3226 device is unity
gain and can be used for analog logic switching and other
applications where unity gain is desired. The ADV3226 outputs
have very high impedance when their outputs are disabled.
The ADV3227 can be used for devices that drive a terminated
cable with its outputs. This device has a built-in gain-of-2 that
eliminates the need for a gain-of-2 buffer to drive a video line. Its
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