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參數(shù)資料
| 型號(hào)： | ADV3202ASWZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 32X16 176LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開(kāi)關(guān) |
| 電路： | 1 x 32:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 5V，±2.5V，±3.3V |
| 電流 - 電源： | 195mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤(pán) |
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ADV3202/ADV3203
Rev. 0 | Page 16 of 20
APPLICATIONS INFORMATION
PROGRAMMING
The ADV3202/ADV3203 are programmed serially through a
193-bit serial word that updates the matrix and the state of the
sync-tip clamps each time the part is programmed.
Serial Programming Description
The serial programming mode uses the CLK, DATA IN,
UPDATE, and CS device pins. The first step is to assert a low
on CS to select the device for programming. The UPDATE
signal should be high during the time that data is shifted into
the serial port of the device. Although the data still shifts in
when UPDATE is low, the transparent, asynchronous latches
allow the shifting data to reach the matrix. This causes the
matrix to try to update to every intermediate state as defined by
the shifting data.
The data at DATA IN is clocked in at every rising edge of CLK.
A total of 193 bits must be shifted in to complete the program-
ming. For each of the 16 outputs, there are five bits (D0 to D4)
that determine the source of its input followed by one bit (D5)
that determines the enabled state of the output. If D5 is low
(output disabled), the five associated bits (D0 to D4) do not
matter because no input is switched to that output. These
comprise the first 96 bits of DATA IN. The remaining 96 bits of
DATA IN should be set to zero. If a string of 96 zeros is not
suffixed to the first 96 bits of DATA IN, a certain test mode is
employed that can cause the device to draw up to 30% more
current. The last bit, Bit 193, is used to enable or disable the
sync-tip clamps. If Bit 193 is low, the sync-tip clamps are
disabled; otherwise, they are enabled.
The sync-tip clamp bit is shifted in first, followed by the most
significant output address data (OUT15). The enable bit (D5) is
shifted in first, followed by the input address (D4 to D0) entered
sequentially with D4 first and D0 last. Each remaining output is
programmed sequentially, until the least significant output
address data is shifted in. At this point, UPDATE can be taken
low, which causes the programming of the device according to
the data that was just shifted in. The UPDATE latches are
asynchronous and when UPDATE is low, they are transparent.
If more than one ADV3202/ADV3203 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
form a serial chain. All of the CLK and UPDATE pins should be
connected in parallel and operated as described previously. The
serial data is input to the DATA IN pin of the first device of the
chain, and it ripples through to the last. Therefore, the data for
the last device in the chain should come at the beginning of the
programming sequence. The length of the programming
sequence is 193 bits times the number of devices in the chain.
Reset
When powering up the ADV3200/ADV3201, it is often useful
to have the outputs come up in the disabled state. The RESET
pin, when taken low, causes all outputs to be disabled. After
power-up, the UPDATE pin should be driven high prior to
raising RESET.
Because the data in the shift register is random after power-up,
it should not be used to program the matrix, or the matrix may
enter unknown states. To prevent this, do not apply a logic low
signal to UPDATE initially after power-up. The shift register
should first be loaded with data and UPDATE then taken low to
program the device.
The RESET pin has a 25 kΩ pull-up resistor to DVCC that can
be used to create a simple power-on reset circuit. A capacitor
from RESET to ground holds RESET low for some time while
the rest of the device stabilizes. The low condition causes all the
outputs to be disabled. The capacitor then charges through the
pull-up resistor to the high state, thus allowing full programming
capability of the device.
The CS pin has a 25 kΩ pull-down resistor to ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV3202-EVALZ | 功能描述:ADV3202 - Interface, Crosspoint Switch/Multiplexer Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:接口，交叉點(diǎn)開(kāi)關(guān)/多路復(fù)用器 嵌入式:- 使用的 IC/零件:ADV3202 主要屬性:32 x 16 視頻交叉點(diǎn)開(kāi)關(guān) 輔助屬性:圖形用戶(hù)界面 所含物品:板，線(xiàn)纜 標(biāo)準(zhǔn)包裝:1 |
| ADV3203 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:300 MHz, 32 × 16 Buffered Analog Crosspoint Switch |
| ADV3203ASWZ | 功能描述:IC CROSSPOINT SWIT 32X16 176LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| ADV3203-EVALZ | 功能描述:ADV3203 - Interface, Crosspoint Switch/Multiplexer Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:接口，交叉點(diǎn)開(kāi)關(guān)/多路復(fù)用器 嵌入式:- 使用的 IC/零件:ADV3203 主要屬性:32 x 16 視頻交叉點(diǎn)開(kāi)關(guān) 輔助屬性:圖形用戶(hù)界面 所含物品:板，線(xiàn)纜 標(biāo)準(zhǔn)包裝:1 |
| ADV3205 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:60 MHz, G = +2, 16 × 16 |
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