
ADV3002
Data Sheet
Rev. B | Page 26 of 28
For example, the maximum speed of signals present on the
auxiliary lines are 100 kHz I2C data on the DDC lines, therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI 1.3a compliance test specification,
however, places a strict 50 pF limit on the amount of capacitance
that can be measured on either SDA or SCL at the HDMI input
connector. The 50 pF limit includes the HDMI connector, the
PCB, and whatever capacitance is seen at the input of the
ADV3002, or an equivalent receiver. There is a similar limit of
150 pF of input capacitance for the CEC line. The benefit of the
ADV3002 is that it buffers these lines, isolating the output
capacitance so that only the capacitance at the input side
contributes to the specified limit.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, make the length of the CEC and DDC lines on the
PCB as short as possible. Additionally, if there is a reference
plane in the layer adjacent to the auxiliary traces in the PCB
stackup, relieving or clearing out this reference plane immediately
under the auxiliary traces significantly decreases the amount of
parasitic trace capacitance. An example of the board stackup is
PCB DIELECTRIC
LAYER 1: SIGNAL (MICROSTRIP)
SILKSCREEN
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
LAYER 3: PWR (REFERENCE PLANE)
LAYER 4: SIGNAL (MICROSTRIP)
W
3W
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
07905-
020
Figure 40. Example Board Stackup for Auxiliary Control Signals
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The trace routing
of this signal is not critical, but it should be routed as directly as
possible.
When the
ADV3002 is powered up, the DDC/CEC inputs of the
selected channel are actively buffered and routed to the outputs,
and the unselected auxiliary inputs are high impedance. When
t
he ADV3002 is powered off, all DDC/CEC inputs are placed in
a high impedance state. This prevents contention on the DDC bus,
enabling a design to include an EDID in front of th
e ADV3002.Power Supplies
The
ADV3002 has two separate power supplies. The supply/
ground pairs are
AVCC/AVEE
AMUXVCC/AVEE
The AVCC/AVEE (3.3 V) supply powers the core of the
ADV3002. The AMUXVCC/AVEE supply (5 V) powers the
auxiliary multiplexer and EDID replication core.
Power Supply Bypassing
The
ADV3002 requires minimal supply bypassing. Generally,
place bypass capacitors near the power pins and connect them
directly to the relevant supplies (without long intervening traces).
For example, to improve the parasitic inductance of the power
supply decoupling capacitors, minimize the trace length between
capacitor landing pads and the vias. The capacitors should via
down directly to the supply planes and should be placed within
Unused DDC/CEC Buffers
If the DDC and the CEC buffers are not used, th
e ADV3002does not require a 5 V supply for AMUXVCC. For operation
without the buffers, tie AMUXVCC to AVCC (nominally 3.3 V).