參數(shù)資料
型號: ADV212BBCZRL-115
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: JPEG 2000 Video Codec
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA121
封裝: 12 X 12 MM, LEAD FREE, MO-192ABD-1, CSPBGA-121
文件頁數(shù): 23/44頁
文件大?。?/td> 374K
代理商: ADV212BBCZRL-115
ADV212
Rev. 0 | Page 23 of 44
121-Ball Package
144-Ball Package
Pins
Used
4
Pin No.
69, 68,
59, 58
57, 46 to 48
Location
G3, G2,
F4, F3
F2, E2, E3,
E4
Pin No.
88,73 to 75
Location
H4, G1 to G3
Mnemonic
HDATA
[23:20]
HDATA
[19:16]
VDATA
[15:12]
Type
I/O
Description
Host Expansion Bus.
76, 61 to 63
G4, F1 to F3
4
I/O
Host Expansion Bus.
I/O
Video Data. Only used for raw pixel video
mode. Unused pins should be pulled down via
a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. This pin must be used
in multiple chip mode to align the outputs of
two or more ADV212s. For details, see the
Applications section and the
AN-796
Application Note
. When not used, this pin
should be tied low via a 10 kΩ resistor.
LCODE Output in Encode Mode. When LCODE
is enabled, the output on this pin indicates on
a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit
interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled
by default.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. This pin should be tied
low via a10 kΩ resistor.
Video Data Clock. This pin must be supplied if
video data is input/output on the VDATA bus.
Video Data. Unused pins should be pulled
down via a 10 kΩ resistor.
112
L2
134
M2
SCOMM7
8
I/O
113
L3
135
M3
SCOMM6
I/O
114
L4
136
M4
SCOMM5
I/O
100
K1
121
L1
SCOMM4
O
101
K2
122
L2
SCOMM3
I
115
L5
123
L3
SCOMM2
O
103
K4
109
K1
SCOMM1
I
102
K3
110
K2
SCOMM0
O
53
E9
60
E12
VCLK
1
I
44, 43, 29,
31, 32, 18 to
20, 22, 21, 7,
10
D11, D10,
C7, C9, C10,
B7, B8, B9,
B11, B10,
A7, A10
D8
46 to 48,
34 to 36,
22 to 24,
9 to 11
D10 to D12,
C10 to C12,
B10 to B12,
A9 to A11
VDATA
[11:0]
12
I/O
41
58
E10
VSYNC
VFRM
1
I/O
Vertical Sync for Video Mode.
Raw Pixel Mode Framing Signal. When this pin
is asserted high, it indicates the first sample of
a tile.
Horizontal Sync for Video Mode.
Raw Pixel Mode Ready Signal.
Field Sync for Video Mode.
Raw Pixel Mode Transfer Strobe.
JTAG Clock. If not used, this pin should be
connected to ground via a pull-down resistor.
JTAG Reset. If the JTAG is used, this pin must
be toggled low to high. If JTAG is not used, this
pin must be held low.
42
54
94
D9
E10
J6
59
57
120
E11
E9
K12
HSYNC
VRDY
FIELD
VSTRB
TCK
1
1
1
I/O
O
I/O
I
I
108
K9
119
K11
TRS
1
I
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