
ADV212
Rev. B | Page 17 of 44
RAW PIXEL MODE TIMING
Table 12.
Parameter
Mnemonic
Min
Typ
Max
Unit
VCLK to PIXELDATA Valid Delay (PIXELDATA Output
)1VDATATD
12
ns
PIXELDATA Setup to Rising VCLK (PIXELDATA Input)
VDATASU
4
ns
PIXELDATA Hold from Rising VCLK (PIXELDATA Input)
VDATAHD
4
ns
VCLK to VRDY Valid Delay
VRDYTD
12
ns
VFRM Setup to Rising VCLK (VFRAME Input)
VFRMSU
3
ns
VFRM Hold from Rising VCLK (VFRAME Input)
VFRMHD
4
ns
VCLK to VFRM Valid Delay (VFRAME Output)
VFRMTD
12
ns
VSTRB Setup to Rising VCLK
VSTRBSU
4
ns
VSTRB Hold from Rising VCLK
VSTRBHD
3
ns
1
PIXELDATA is the actual data on the VDATA bus; pins and bus width depend on it but timing does not.
RAW PIXEL MODE—ENCODE
VCLK
PIXEL 1
PIXEL 2
PIXEL 3
VSTRBHD
VFRMSU
VFRMHD
VRDYTD
VSTRBSU
VDATAHD
VDATASU
VFRM (IN)
VSTRB (IN)
VRDY (OUT)
PIXELDATA (IN)
RAW PIXEL MODE—DECODE
VCLK
PIXEL 1
PIXEL 2
PIXEL 3
VSTRBSU
VSTRBHD
VFRMTD
VDATATD
VRDYTD
VFRM (OUT)
VSTRB (IN)
VRDY (OUT)
PIXELDATA (OUT)
06389-
031
Figure 28. Raw Pixel Modes