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參數(shù)資料
| 型號(hào)： | ADV212 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 視頻Codec |
| 英文描述： | JPEG 2000 Video Codec |
| 中文描述： | JPEG 2000視頻編解碼器 |
| 文件頁數(shù)： | 27/44頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ADV212 |
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ADV212
CONTROL ACCESS REGISTERS
With the exception of the indirect address and data registers
(IADDR and IDATA), all control/status registers in the
ADV212 are 16 bits wide and are half-word (16-bit) addressable
only. When 32-bit host mode is enabled, the upper 16 bits of the
HDATA bus are ignored on writes and return all zeros on reads
of 16-bit registers.
PIN CONFIGURATION AND BUS SIZES/MODES
The ADV212 provides a wide variety of control and data
configurations, which allows it to be used in many applications
with little or no glue logic. The modes described in this section
are configured using the BUSMODE register. In this section,
host
refers to normal addressed accesses (CS/RD/WE/ADDR)
and
data
refers to external DMA accesses (DREQ/DACK).
32-Bit Host/32-Bit Data
In this mode, the HDATA<31:0> pins provide full 32-bit wide
data access to PIXEL, CODE, ATTR FIFOs.
16-Bit Host/32-Bit Data
This mode allows a 16-bit host to configure and communicate
with the ADV212 while allowing 32-bit accesses to the PIXEL,
CODE, ATTR FIFOs using the external DMA capability.
All addressed host accesses are 16 bits and, therefore, use only
the HDATA<15:0> pins. The HDATA<31:16> pins provide the
additional 16 bits necessary to support the 32-bit external DMA
transfers to and from the FIFOs only.
16-Bit Host/16-Bit Data
This mode uses 16-bit transfers if used for host or external
DMA data transfers.
16-Bit Host/8-Bit Data (JDATA Bus Mode)
This mode provides separate data input/output and host
control interface pins. Host control accesses are 16 bits and use
HDATA<15:0>, whereas the dedicated data bus uses JDATA<7:0>.
JDATA uses a valid/hold synchronous transfer protocol. The
direction of the JDATA bus is determined by the mode of the
ADV212. If the ADV212 is encoding (compression),
JDATA<7:0> is an output. If the ADV212 is decoding
(decompression), JDATA<7:0> is an input. Host control
accesses remain asynchronous. See also JDATA section below.
STAGE REGISTER
Because the ADV212 contains both 16-bit and 32-bit registers
and its internal memory is mapped as 32-bit data, a mechanism
Rev. 0 | Page 27 of 44
has been provided to allow 16-bit hosts to access these registers
and memory locations using the stage register (STAGE). STAGE
is accessed as a 16-bit register using HDATA [15:0]. Prior to
writing to the desired register, the stage register must be written
with the upper (most significant) half-word.
When the host subsequently writes the lower half-word to the
desired control register, HDATA is combined with the
previously staged value to create the required 32-bit value that is
written. When a register is read, the upper (most significant)
half-word is returned immediately on HDATA and the lower
half-word can be retrieved by reading the stage register on a
subsequent access. For details on using the stage register, see the
ADV212 User’s Guide
.
Note that the stage register does not apply to the three data
channels (PIXEL, CODE, ATTR). These channels are always
accessed at the specified data width and do not require the use
of the stage register.
JDATA MODE
JDATA mode is typically used only when the dedicated video
interface (VDATA) is also enabled. This mode allows code
stream data (compressed data compliant with JPEG 2000) to be
input or output on a single dedicated 8-bit bus (JDATA<7:0>).
The bus is always an output during compression operations,
and is an input during decompression.
A 2-pin handshake is used to transfer data over this
synchronous interface. VALID is used to indicate that the
ADV212 is ready to provide or accept data and is always an
output. HOLD is always an input and is asserted by the host if it
cannot accept/provide data. For example, JDATA mode allows
real-time applications, in which pixel data is input over the
VDATA bus while the compressed data stream is output over
the JDATA bus.
EXTERNAL DMA ENGINE
The external DMA interface is provided to enable high
bandwidth data input/output between an external DMA
controller and the ADV212 data FIFOs. Two independent DMA
channels can each be assigned to any one of the three data
stream FIFOs (PIXEL, CODE, ATTR).
The controller supports asynchronous DMA using a
data-request/data-acknowledge (DREQ/DACK) protocol in
either single or burst access modes. Additional functionality is
provided for single address compatibility (fly-by) and dedicated
chip select (DCS) modes.
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PDF描述 |
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| ADV212BBCZ-115 | JPEG 2000 Video Codec |
| ADV212BBCZ-150 | JPEG 2000 Video Codec |
| ADV212BBCZRL-115 | JPEG 2000 Video Codec |
| ADV212BBCZRL-150 | JPEG 2000 Video Codec |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV212-ASD-P160-EB | 制造商:Analog Devices 功能描述: |
| ADV212-ASD-P160EBZ | 制造商:Analog Devices 功能描述:VID CODEC - Bulk |
| ADV212BBCZ-115 | 功能描述:IC CODEC VID JPEG 2000 121CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:Wavescale® 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADV212BBCZ-150 | 功能描述:IC CODEC VID JPEG 2000 144CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:Wavescale® 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| ADV212BBCZRL-115 | 功能描述:IC CODEC VID JPEG 2000 121CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:Wavescale® 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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