參數(shù)資料
型號(hào)： ADUC842BCPZ8-3
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/88頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8KB FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 8.38MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： DMA，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
包裝： 托盤(pán)
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 41 of 88
ON-CHIP PLL
The ADuC842 and ADuC843 are intended for use with a
32.768 kHz watch crystal. A PLL locks onto a multiple (512) of
this to provide a stable 16.78 MHz clock for the system. The
ADuC841 operates directly from an external crystal. The core
can operate at this frequency or at binary submultiples of it to
allow power saving in cases where maximum core performance
is not required. The default core clock is the PLL clock divided
by 8 or 2.097152 MHz. The ADC clocks are also derived from
the PLL clock, with the modulator rate being the same as the
crystal oscillator frequency. The preceding choice of frequencies
ensures that the modulators and the core are synchronous,
regardless of the core clock rate. The PLL control register is
PLLCON.
At 5 V the core clock can be set to a maximum of 16.78 MHz,
while at 3 V the maximum core clock setting is 8.38 MHz. The
CD bits should not be set to 0 on a 3 V part.
Note that on the ADuC841, changing the CD bits in PLLCON
causes the core speed to change. The core speed is crystal freq/
2CD. The other bits in PLLCON are reserved in the case of the
ADuC841 and should be written with 0.
PLLCON PLL
Control Register
SFR Address
D7H
Power-On Default
53H
Bit Addressable
No
Table 16. PLLCON SFR Bit Designations
Bit No.
Name
Description
7
OSC_PD
Oscillator Power-Down Bit.
Set by the user to halt the 32 kHz oscillator in power-down mode.
Cleared by the user to enable the 32 kHz oscillator in power-down mode.
This feature allows the TIC to continue counting even in power-down mode.
6
LOCK
PLL Lock Bit.
This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external
crystal subsequently becomes disconnected, the PLL will rail.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due
to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 16.78 MHz
±20%.
5
----
Reserved. Should be written with 0.
4
----
Reserved. Should be written with 0.
3
FINT
Fast Interrupt Response Bit.
Set by the user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless
of the configuration of the CD2–0 bits (see below). Once user code has returned from an interrupt, the core resumes
code execution at the core clock selected by the CD2–0 bits.
Cleared by the user to disable the fast interrupt response feature.
2
CD2
CPU (Core Clock) Divider Bits.
1
CD1
This number determines the frequency at which the microcontroller core operates.
0
CD0
CD2
0
1
CD1
0
1
0
1
CD0
0
1
0
1
0
1
0
1
Core Clock Frequency (MHz)
16.777216
8.388608
4.194304
2.097152 (Default Core Clock Frequency)
1.048576
0.524288
0.262144
0.131072
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