參數(shù)資料
型號(hào)： ADUC842BCPZ32-3
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/88頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 8.38MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： DMA，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 27 of 88
The ADC incorporates a successive approximation architecture
(SAR) involving a charge-sampled input stage. Figure 30 shows
the equivalent circuit of the analog input section. Each ADC
conversion is divided into two distinct phases, as defined by the
position of the switches in Figure 30. During the sampling
phase (with SW1 and SW2 in the track position), a charge
proportional to the voltage on the analog input is developed
across the input sampling capacitor. During the conversion
phase (with both switches in the hold position), the capacitor
DAC is adjusted via internal SAR logic until the voltage on
Node A is 0, indicating that the sampled charge on the input
capacitor is balanced out by the charge being output by the
capacitor DAC. The final digital value contained in the SAR is
then latched out as the result of the ADC conversion. Control of
the SAR and timing of acquisition and sampling modes is
handled automatically by built-in ADC control logic.
Acquisition and conversion times are also fully configurable
under user control.
CAPACITOR
DAC
COMPARATOR
VREF
AGND
DAC1
DAC0
TEMPERATURE MONITOR
AIN7
AIN0
32pF
AGND
ADuC841/ADuC842/ADuC843
NODE A
sw1
sw2
TRACK
HOLD
200
200
03260-0-028
Figure 30. Internal ADC Structure
Note that whenever a new input channel is selected, a residual
charge from the 32 pF sampling capacitor places a transient on
the newly selected input. The signal source must be capable of
recovering from this transient before the sampling switches go
into hold mode. Delays can be inserted in software (between
channel selection and conversion request) to account for input
stage settling, but a hardware solution alleviates this burden
from the software design task and ultimately results in a cleaner
system implementation. One hardware solution is to choose a
very fast settling op amp to drive each analog input. Such an op
amp would need to fully settle from a small signal transient in
less than 300 ns in order to guarantee adequate settling under
all software configurations. A better solution, recommended for
use with any amplifier, is shown in Figure 31. Though at first
glance the circuit in Figure 31 may look like a simple antialias-
ing filter, it actually serves no such purpose since its corner
frequency is well above the Nyquist frequency, even at a 200
kHz sample rate. Though the R/C does help to reject some
incoming high frequency noise, its primary function is to ensure
that the transient demands of the ADC input stage are met.
AIN0
ADuC841/
ADuC842/
ADuC843
10
0.1
F
03260-0-029
Figure 31. Buffering Analog Inputs
It does so by providing a capacitive bank from which the 32 pF
sampling capacitor can draw its charge. Its voltage does not
change by more than one count (1/4096) of the 12-bit transfer
function when the 32 pF charge from a previous channel is
dumped onto it. A larger capacitor can be used if desired, but
not a larger resistor (for reasons described below). The Schottky
diodes in Figure 31 may be necessary to limit the voltage
applied to the analog input pin per the Absolute Maximum
Ratings. They are not necessary if the op amp is powered from
the same supply as the part since in that case the op amp is
unable to generate voltages above VDD or below ground. An op
amp of some kind is necessary unless the signal source is very
low impedance to begin with. DC leakage currents at the parts’
analog inputs can cause measurable dc errors with external
source impedances as low as 100 or so. To ensure accurate
ADC operation, keep the total source impedance at each analog
input less than 61 . The Table 10 illustrates examples of how
source impedance can affect dc accuracy.
Table 10. Source Impedance and DC Accuracy
Source
Impedance
Error from 1 A
Leakage Current
Error from 10 A
Leakage Current
61
61 V = 0.1 LSB
610 V = 1 LSB
610
610 V = 1 LSB
6.1 mV = 10 LSB
Although Figure 31 shows the op amp operating at a gain of 1,
one can, of course, configure it for any gain needed. Also, one
can just as easily use an instrumentation amplifier in its place to
condition differential signals. Use an amplifier that is capable of
delivering the signal (0 V to VREF) with minimal saturation.
Some single-supply rail-to-rail op amps that are useful for this
purpose are described in Table 11. Check Analog Devices website
www.analog.com for details on these and other op amps and
instrumentation amps.
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