參數(shù)資料
型號: ADUC841BCPZ8-3
廠商: Analog Devices Inc
文件頁數(shù): 19/88頁
文件大?。?/td> 0K
描述: IC MCU 8KB FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 8.38MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: DMA,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 托盤
配用: EVAL-ADUC841QSZ-ND - KIT DEV FOR ADUC841 QUICK START
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 26 of 88
ADCCON3—(ADC Control SFR 3)
The ADCCON3 register controls the operation of various
calibration modes and also indicates the ADC busy status.
SFR Address
F5H
SFR Power-On Default
00H
Bit Addressable
No
Table 9. ADCCON3 SFR Bit Designations
Bit No.
Name
Description
7
BUSY
ADC Busy Status Bit.
A read-only status bit that is set during a valid ADC conversion or during a calibration cycle.
Busy is automatically cleared by the core at the end of conversion or calibration.
6
RSVD
Reserved. This bit should always be written as 0.
5
AVGS1
Number of Average Selection Bits.
This bit selects the number of ADC readings that are averaged during a calibration cycle.
4
AVGS0
AVGS1
0
1
AVGS0
0
1
0
1
Number of Averages
15
1
31
63
3
RSVD
Reserved. This bit should always be written as 0.
2
RSVD
This bit should always be written as 1 by the user when performing calibration.
1
TYPICAL
Calibration Type Select Bit.
This bit selects between offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for offset calibration.
Set to 1 for gain calibration.
0
SCAL
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle.
It is automatically cleared when the calibration cycle is completed.
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