參數(shù)資料
型號(hào)： ADUC836BS
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
中文描述： 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝： 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁數(shù)： 61/80頁
文件大?。?/td> 5913K
代理商： ADUC836BS
ADuC836
–61–
INTERRUPT SYSTEM
The ADuC836 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system
are carried out through three interrupt-related SFRs: the IE (Interrupt Enable) Register, IP (Interrupt Priority Register), and IEIP2
(Secondary Interrupt Enable/Priority SFR) Registers. Their bit definitions are given in the Tables XXXV to XXXVII.
IE Interrupt Enable Register
SFR Address A8H
Power-On Default Value 00H
Bit Addressable Yes
Table XXXV. IE SFR Bit Designations
Bit Name Description
7 EA Written by User to Enable 1 or Disable 0 All Interrupt Sources
6 EADC Written by User to Enable 1 or Disable 0 ADC Interrupt
5 ET2 Written by User to Enable 1 or Disable 0 Timer 2 Interrupt
4 ES Written by User to Enable 1 or Disable 0 UART Serial Port Interrupt
3 ET1 Written by User to Enable 1 or Disable 0 Timer 1 Interrupt
2 EX1 Written by User to Enable 1 or Disable 0 External Interrupt 1
1 ET0 Written by User to Enable 1 or Disable 0 Timer 0 Interrupt
0 EX0 Written by User to Enable 1 or Disable 0 External Interrupt 0
IP Interrupt Priority Register
SFR Address B8H
Power-On Default Value 00H
Bit Addressable Yes
Table XXXVI. IP SFR Bit Designations
Bit Name Description
7 ––– Reserved for Future Use
6 PADC Written by User to Select ADC Interrupt Priority (1 = High; 0 = Low)
5 PT2 Written by User to Select Timer 2 Interrupt Priority (1 = High; 0 = Low)
4 PS Written by User to Select UART Serial Port Interrupt Priority (1 = High; 0 = Low)
3 PT1 Written by User to Select Timer 1 Interrupt Priority (1 = High; 0 = Low)
2 PX1 Written by User to Select External Interrupt 1 Priority (1 = High; 0 = Low)
1 PT0 Written by User to Select Timer 0 Interrupt Priority (1 = High; 0 = Low)
0 PX0 Written by User to Select External Interrupt 0 Priority (1 = High; 0 = Low)
IEIP2 Secondary Interrupt Enable and
Priority Register
SFR Address A9H
Power-On Default Value A0H
Bit Addressable No
Table XXXVII. IEIP2 SFR Bit Designations
Bit Name Description
7 ––– Reserved for Future Use
6 PTI Written by User to Select TIC Interrupt Priority (1 = High; 0 = Low)
5 PPSM Written by User to Select Power Supply Monitor Interrupt Priority (1 = High; 0 = Low)
4 PSI Written by User to Select SPI/I
2
C Serial Port Interrupt Priority (1 = High; 0 = Low)
3 ––– Reserved. This bit must be 0.
2 ETI Written by User to Enable 1 or Disable 0 TIC Interrupt
1 EPSM Written by User to Enable 1 or Disable 0 Power Supply Monitor Interrupt
0 ESI Written by User to Enable 1 or Disable 0 SPI/I
2
C Serial Port Interrupt
REV. A
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參數(shù)描述
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