參數(shù)資料
型號： ADUC836BCP
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
中文描述： 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封裝： 8 X 8 MM, ROHS COMPLIANT, MO-220-VLLD-2, LFCSP-56
文件頁數(shù)： 54/80頁
文件大小： 5913K
代理商： ADUC836BCP
ADuC836
–54–
TIMER/COUNTER 0 AND 1 OPERATING MODES
The following paragraphs describe the operating modes for Timer/
Counters 0 and 1. Unless otherwise noted, it should be assumed
that these modes of operation are the same for both Timer 0 and 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32
prescaler. Figure 48 shows Mode 0 operation.
12
CORE
CLK
*
CONTROL
P3.4/T0
GATE
P3.2/
INT0
TR0
TF0
TL0
(5 BITS)
TH0
(8 BITS)
INTERRUPT
C/
T
= 0
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
C/
T
= 1
Figure 48. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer over-
flow flag. The overflow flag, TF0, can then be used to request an
interrupt. The counted input is enabled to the timer when TR0 = 1
and either Gate = 0 or
INT0
= 1. Setting Gate = 1 allows the
timer to be controlled by external input
INT0
to facilitate pulse-
width measurements. TR0 is a control bit in the special function
register TCON; Gate is in TMOD. The 13-bit register consists
of all eight bits of TH0 and the lower five bits of TL0. The upper
three bits of TL0 are indeterminate and should be ignored. Setting
the run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. Mode 1 is shown in Figure 49.
12
CORE
CLK
*
CONTROL
P3.4/T0
GATE
P3.2/
INT0
TR0
TF0
TL0
(8 BITS)
TH0
(8 BITS)
INTERRUPT
C/
T
= 0
C/
T
= 1
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 49. Timer/Counter 0, Mode 1
Mode 2 (8-Bit Timer/Counter with Auto Reload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 50. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which are preset by software. The reload leaves TH0 unchanged.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
RELOAD
TH0
(8 BITS)
12
CORE
CLK
*
P3.4/T0
GATE
P3.2/
INT0
TR0
C/
T
= 0
C/
T
= 1
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 50. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 51. TL0
uses the Timer 0 control bits: C/
T
, Gate, TR0,
INT0
, and TF0.
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0
now controls the Timer 1 interrupt. Mode 3 is provided for appli-
cations requiring an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off by
switching it out of and into its own Mode 3, or it can still be used by
the serial interface as a baud rate generator. In fact, it can be used in
any application not requiring an interrupt from Timer 1 itself.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
12
CORE
CLK
*
P3.4/T0
GATE
P3.2/
INT0
TR0
C/
T
= 0
C/
T
= 1
CORE
TF1
TH0
(8 BITS)
INTERRUPT
CORE
CLK/12
TR1
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 51. Timer/Counter 0, Mode 3
REV. A
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