參數(shù)資料
型號(hào)： ADUC824BSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/68頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
REV. B
ADuC824
–36–
Figure 22 shows the frequency response of the ADC chan-
nel at the default SF word of 69 dec or 45 hex, yielding an
overall output update rate of just under 20 Hz.
It should be noted that this frequency response allows frequency
components higher than the ADC Nyquist frequency to pass
through the ADC, in some cases without significant attenuation.
These components may, therefore, be aliased and appear in-band
after the sampling process.
It should also be noted that rejection of mains-related frequency
components, i.e., 50 Hz and 60 Hz, is seen to be at level of
>65 dB at 50 Hz and >100 dB at 60 Hz. This confirms the
data sheet specifications for 50 Hz/60 Hz Normal Mode Rejec-
tion (NMR) at a 20 Hz update rate.
0
20
30
50
70
80
90
100
110
FREQUENCY – Hz
GAIN
–
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
10
40
60
–10
–30
–60
–50
Figure 22. Filter Response, SF = 69 dec
The response of the filter, however, will change with SF word as
can be seen in Figure 23, which shows >90 dB NMR at 50 Hz
and >70 dB NMR at 60 Hz when SF = 255 dec.
0
20
30
50
70
80
90
100
FREQUENCY – Hz
GAIN
–
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
10
40
60
–10
–30
–60
–50
Figure 23. Filter Response, SF = 255 dec
Figures 24 and 25 show the NMR for 50 Hz and 60 Hz across
the full range of SF word, i.e., SF = 13 dec to SF = 255 dec.
10
50
70
110
150 170 190 210
SF – Decimal
GAIN
–
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
30
90
130
–10
–30
–60
–50
230 250
Figure 24. 50 Hz Normal Mode Rejection vs. SF
10
50
70
110
150 170 190 210
SF – Decimal
GAIN
–
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
30
90
130
–10
–30
–60
–50
230 250
Figure 25. 60 Hz Normal Mode Rejection vs. SF
ADC Chopping
Both ADCs on the ADuC824 implement a chopping scheme
whereby the ADC repeatability reverses its inputs. The deci-
mated digital output words from the Sinc
3 filters therefore have a
positive offset and negative offset term included.
As a result, a final summing stage is included in each ADC so that
each output word from the filter is summed and averaged with the
previous filter output to produce a new valid output result to be
written to the ADC data SFRs. In this way, while the ADC
throughput or update rate is as discussed earlier and illustrated
in Table VII, the full settling time through the ADC (or the time
to a first conversion result), will actually be given by 2
× tADC.
The chopping scheme incorporated in the ADuC824 ADC results
in excellent dc offset and offset drift specifications and is
extremely beneficial in applications where drift, noise rejection,
and optimum EMI rejection are important factors.
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