參數(shù)資料
型號(hào)： ADUC814BRU-REEL7
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Circular Connector; No. of Contacts:61; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:25-61
中文描述： 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28
封裝： 4.40 X 9.70 MM, MO-153AE, TSSOP-28
文件頁數(shù)： 58/72頁
文件大小： 846K
代理商： ADUC814BRU-REEL7
ADuC814
IP
SFR Address
Power-On Default
Bit Addressable
---
Rev. A | Page 58 of 72
Interrupt Priority Register
B8H
00H
Yes
PADC
PT2
PS
PT1
PX1
PT0
PX0
Table 30. IP SFR Bit Designations
Bit No.
Name
7
---
6
PADC
Description
Reserved.
ADC Interrupt Priority.
Written to by user to set interrupt priority level (1 = High; 0 = Low).
Timer 2 Interrupt Priority.
Written to by the user to set interrupt priority level (1 = High; 0 = Low).
UART Serial Port Interrupt Priority.
Written to by the user to set interrupt priority level (1 = High; 0 = Low).
Timer 1 Interrupt Priority.
Written to by the user to set interrupt priority level (1 = High; 0 = Low).
External Interrupt 1 Priority (INT1).
Written to by the user to set interrupt priority level (1 = High; 0 = Low).
Timer 0 Interrupt Priority.
Written to by the user to set interrupt priority level (1 = High; 0 = Low).
External Interrupt 0 Priority (INT0).
Written to by the user to set interrupt priority level (1 = High; 0 = Low).
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
IEIP2
SFR Address
Power-On Default
Bit Addressable
---
Secondary Interrupt Enable and Priority Register
A9H
A0H
No
PT1
PPSM
PSI
---
ETI
EPSM
ESI
Table 31. IEIP2 SFR Bit Designations
Bit No.
Name
7
---
6
PTI
Description
Reserved.
Time Interval Counter Interrupt Priority.
Written to by the user to set TIC interrupt priority (1 = High; 0 = Low).
PSM Interrupt Priority.
Written to by the user to select power supply monitor interrupt priority (1 = High; 0 = Low).
SPI Serial Port Interrupt Priority.
Written to by the user to select SPI serial port interrupt priority (1 = High; 0 = Low).
Reserved. This bit must be 0.
TIC Interrupt.
Set by the user to enable the TIC interrupt.
Cleared by the user to disable the TIC interrupt.
Power Supply Monitor Interrupt.
Set by the user to enable the power supply monitor interrupt.
Cleared by the user to disable the power supply monitor interrupt.
SPI Serial Port Interrupt.
Set by the user to enable the SPI serial port interrupt.
Cleared by the user to disable the SPI serial port interrupt.
5
PPSM
4
PSI
3
2
---
ETI
1
EPSM
0
ESI
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