參數(shù)資料
型號： ADUC812BS-REEL
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MSC-51 8K-Flash/256-RAM/640-EEPROM(543.84 k)
中文描述： 8-BIT, FLASH, 11.0592 MHz, MICROCONTROLLER, PQFP52
封裝： MQFP-52
文件頁數(shù)： 20/31頁
文件大?。?/td> 543K
代理商： ADUC812BS-REEL
REV. 0
ADuC812
–
20
–
TH2, TL2
TIMER2 REGISTER
RCAP2H, RCAP2L
TIMER2 CAPTURE/RELOAD
TF2
EXF2
RCLK
OVERFLOW FLAG
EXTERNAL FLAG
RECEIVE CLOCK ENABLE
(0 = TIMER1 USED FOR RxD CLK)
TRANSMIT CLOCK ENABLE
(0 = TIMER1 USED FOR TxD CLK)
EXEN2 EXTERNAL ENABLE
(0 = IGNORE T2EX, 1 = CAP/RL)
TR2
RUN CONTROL (0 = STOP, 1 = RUN)
CNT2
TIMER/COUNTER SELECT
(0 = TIMER, 1 = COUNTER)
CAP2
CAPTURE/RELOAD SELECT
(0 = RELOAD, 1 = CAPTURE)
TCLK
T2CON
TIMER2 CONTROL REGISTER
TH0, TL0
TH1, TL1
TIMER0 REGISTERS
TIMER1 REGISTERS
TF1
TIMER1 OVERFLOW FLAG
(AUTO CLEARED ON VECTOR TO ISR)
TIMER1 RUN CONTROL (0 = OFF, 1 = RUN)
TIMER0 OVERFLOW FLAG
(AUTO CLEARED ON VECTOR TO ISR)
TIMER0 RUN CONTROL (0 = OFF, 1 = RUN)
EXTERNAL INT1 FLAG
(AUTO CLEARED ON VECTOR TO ISR)
IE1 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
EXTERNAL INT0 FLAG
(AUTO CLEARED ON VECTOR TO ISR)
IE0 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON
TIMER CONTROL REGISTER
PSI
PRIORITY OF ISI/ISPI
(SERIAL INTERFACE INTERRUPT)
PRIORITY OF ADCI (ADC INTERRUPT)
PRIORITY OF TF2/EXF2
(TIMER2 OVERFLOW INTERRUPT)
PRIORITY OF RI/TI (SERIAL PORT INTERRUPT)
PRIORITY OF TF1
(TIMER1 OVERFLOW INTERRUPT)
PRIORITY OF IE1 (EXTERNAL INT1)
PRIORITY OF TF0
(TIMER0 OVERFLOW INTERRUPT)
PRIORITY OF IE0 (EXTERNAL INT0)
PADC
PT2
PS
PT1
PX1
PT0
PX0
TMOD
IP
INTERRUPT PRIORITY REGISTER
IE2.1
ENABLE PSMI
(POWER SUPPLY MONITOR INTERRUPT)
ENABLE ISPI/I2CI
(SERIAL INTERFACE INTERRUPT)
IE2.0
IE2
INTERRUPT ENABLE REGISTER #2
EA
ENABLE INTURRUPTS
(0 = ALL INTERRUPTS DISABLED)
EADC ENABLE ADCI (ADC INTERRUPT)
ET2
ENABLE TF2/EXF2
(TIMER2 OVERFLOW INTERRUPT)
ES
ENABLE RI/TI (SERIAL PORT INTERRUPT)
ET1
ENABLE TF1 (TIMER1 OVERFLOW INTERRUPT)
EX1
ENABLE IE1 (EXTERNAL INTERRUPT 1)
ET0
ENABLE TFO (TIMER0 OVERFLOW INTERRUPT)
EX0
ENABLE IE0 (EXTERNAL INTERRUPT 0)
IE
INTERRUPT ENABLE REGISTER #1
TMOD.3/.7
TMOD.2/.6
TMOD.1/.5
TMOD.0/.4 TIMER MODE SELECTON BITS
2 8 BIT T]
(UPPER NIBBLE = TIMER1, LOWER NIBBLE = TIMER2)
GATE CONTROL BIT (0 = IGNORE INTx)
COUNTER/TIMER SELECT BIT (0 = TIMER)
TIMER MODE REGISTER
ISPI
SPI INTERRUPT
(SET AT END OF SPI TRANSFER)
WRITE COLLISION ERROR FLAG
SPI ENABLE
(0 = DISABLE, ALSO ENABLES SPI)
MASTER MODE SELECT (0 = SLAVE)
CLOCK POLARITY SELECT
(0 = SCLK IDLES LOW)
CLOCK PHASE SELECT
(0 = LEADING EDGE LATCH)
SPI BITRATE SELECT BITS
BITRATE = F
OSC
/ [4, 8, 32, 64]
SPIDAT
SPI DATA REGISTER
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
SPICON
SPI CONTROL REGISTER
MDO
MDE
MASTER MODE SDATA OUTPUT BIT
MASTER MODE SDATA OUTPUT
ENABLE
MASTER MODE SCLK BIT
MASTER MODE SDATA INPUT BIT
MASTER MODE SELECT
SERIAL PORT RESET
TRANSMISSION DIRECTION STATUS
SERIAL INTERFACE INTERRUPT
MCO
MDI
I
2
CM
I
2
CRS
I
2
CTX
I
2
CI
I2CCON
I
2
C CONTROL REGISTER
I2CADD
I
2
C ADDRESS REGISTER
I2CDAT
I
2
C DATA REGISTER
Figure 19. Interrupt, Timer, SPI and I
2
C Control SFRs
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