參數(shù)資料
型號(hào): ADUC812
廠商: Analog Devices, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; MIL SPEC:MIL-DTL-38999 Series I; Body Material:Metal; Series:LJT; No. of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight RoHS Compliant: No
中文描述: MicroConverter的⑩,多通道12位ADC,嵌入式閃存MCU
文件頁(yè)數(shù): 16/31頁(yè)
文件大?。?/td> 543K
代理商: ADUC812
REV. 0
ADuC812
16
Bit
Location
Bit
Mnemonic
Description
IE.1
ET0
The Timer 0 Overflow Interrupt
Enable bit (ET0) is set to “1” to
enable the Timer 0 interrupt.
The INT0 Interrupt Enable bit
(EX0) is set to “1” to enable the
external INT0 interrupt
IE.0
EX0
IE2 – (Interrupt Enable 2 SFR )
The IE2 register enables two additional interrupt sources.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
A9H
00H
NO
NU
NU
NU
NU
NU
NU
EPSM ESI
Table IX. Interrupt Enable 2 (IE2) SFR Bit Designations
Bit
Location
Bit
Mnemonic
Description
IE2.7
IE2.6
IE2.5
IE2.4
IE2.3
IE2.2
IE2.1
NU
NU
NU
NU
NU
NU
EPSM
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
The Power Supply Monitor
Interrupt enable bit is set to “1”
to enable the PSM Interrupt.
The SPI/I
2
C Interrupt Enable bit
(ESI) is set to “1” to enable the
SPI or I
2
C interrupt.
IE2.0
ESI
IP – (Interrupt Priority SFR )
The IP register sets one of two main priority levels for the vari-
ous interrupt sources. Set the corresponding bit to “1” to con-
figure interrupt as high priority and to “0” to configure interrupt
as low priority.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
B8H
00H
YES
PS1
PADC
PT2
PS
PT1
PX1
PT0
PX0
Table X. Interrupt Priority (IP) SFR Bit Designations
Bit
Location
Bit
Mnemonic
Description
IP.7
IP.6
IP.5
IP.4
PSI
PADC
PT2
PS
Sets SPI/I
2
C Interrupt Priority
Sets ADC Interrupt Priority
Sets Timer 2 Interrupt Priority
Sets UART Serial Port Interrupt
Priority
Sets Timer 1 Interrupt Priority
Sets External INT1 Interrupt
Priority
Sets Timer 0 Interrupt Priority
Sets External INT0 Interrupt
Priority
IP.3
IP.2
PT1
PX1
IP.1
IP.0
PT0
PX0
Table VII. Interrupt Vector Addresses
Interrupt
Vector
Address
Priority
Within
Level
Interrupt
Interrupt Name
PSMI
IE0
ADCI
TF0
IE1
TF1
I2CI/ISPI
RI/TI
TF2/EXF2
Power Supply Monitor
External
INT0
End of ADC Conversion
Timer 0 Overflow
External
INT1
Timer 1 Overflow
Serial Interrupt
UART Interrupt
Timer 2 Interrupt
43H
03H
33H
0BH
13H
1BH
3BH
23H
2BH
1
2
3
4
5
6
7
8
9
Use of Interrupts
To use any of the interrupts on the ADuC812, the following
three steps must be taken.
1. Locate the interrupt service routine at the corresponding
Vector Address of that interrupt. See Table VII above.
2. Set the EA (enable all) bit in the IE SFR to “1.”
3. Set the corresponding individual interrupt bit in the IE
or IE2 SFR to “1.”
Three SFRs are used to enable and set priority for the various
interrupts. The bit designations of these SFRs are shown in
Tables VIII, IX and X. It should be noted that while IE and IP
SFRs are bit addressable, IE2 is byte addressable only.
IE – (Interrupt Enable SFR)
The IE register enables the interrupt system and seven interrupt
sources.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
A8H
00H
YES
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
Table VIII. Interrupt Enable (IE) SFR Bit Designations
Bit
Location
Bit
Mnemonic
Description
IE.7
EA
The Global Interrupt Enable bit
(EA) must be set to “1” before any
interrupt source will be recognized
by the core. EA is set to “0” to dis-
able all interrupts.
The ADC Interrupt Enable bit
(EADC) is set to “1” to enable the
ADC interrupt.
The Timer 2 Overflow Interrupt
Enable bit (ET2) is set to “1” to
enable the Timer 2 interrupt.
The UART Serial Port Interrupt
Enable bit (ES) is set to “1” to en-
able the UART Serial Port Interrupt.
The Timer 1 Overflow Interrupt
Enable bit (ET1) is set to “1” to
enable the Timer 1 interrupt.
The INT1 Interrupt Enable bit
(EX1) is set to “1” to enable the
external INT1 interrupt.
IE.6
EADC
IE.5
ET2
IE.4
ES
IE.3
ET1
IE.2
EX1
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