參數(shù)資料
型號(hào)： ADuC812(中文)
廠商： Analog Devices, Inc.
英文描述： 12-Bit ADC with Embedded FLASH MCU(12位8通道A/D轉(zhuǎn)換器)
中文描述： 12位ADC，嵌入式閃存微控制器（12位8通道的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 34/35頁(yè)
文件大?。?/td> 926K
代理商： ADUC812(中文)
==
99-9-30==
P&S
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==35-34==
P &S
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430079
μ°:
( 86) ( 027￡87493500 87493506
′
( 86) ( 027) 87491166, 87493497
P &S
í í :
http://www.p8s.com
B
SP
STACK POINTER
ACC
ACCUMULATOR
CY
AC
F0
RS1
CARRY FLAG
AUXILIARY CARRY FLAG
GENERAL PURPOSE FLAG 0
REGISTER BANK SELECT
CONTROL BITS
ACTIVE REGISTER BANK = [0, 1, 2, 3]
OVERFLOW FLAG
GENERAL PURPOSE FLAG 1
PARITY OF ACC
DPP
DATA POINTER PAGE
RS0
OV
F1
P
PSW
PROGRAM STATUS WORD
SBUF
SERIAL PORT BUFFER REGISTER
PCON
POWER CONTROL REGISTER
PCON.7
PCON.4
DOUBLE BAUD RATE CONTROL
ALE DISABLE
(0 = NORMAL, 1 = FORCES ALE HIGH)
PCON.3 GENERAL PURPOSE FLAG
PCON.2 GENERAL PURPOSE FLAG
PCON.1 POWER-DOWN CONTROL BIT
(RECOVERABLE WITH HARD RESET)
PCON.0 IDLE-MODE CONTROL
(RECOVERABLE WITH ENABLED
INTERRUPT)
DPH, DPL (DPTR)
DATA POINTER
EXTERNAL DATA MEMORY READ STROBE
EXTERNAL DATA MEMORY WRITE STROBE
TIMER/COUNTER 1 EXTERNAL INPUT
TIMER/COUNTER 0 EXTERNAL INPUT
EXTERNAL INTERRUPT 1
EXTERNAL INTERRUPT 0
SERIAL PORT TRANSMIT DATA LINE
SERIAL PORT RECEIVE DATA LINE
T1
T0
TxD
RxD
P3
PORT3 REGISTER
SM0
SM1
UART MODE CONTROL BITS BAUD RATE:
00 - 8 BIT SHIFT REGISTER F
/12
01 - 8 BIT UART
TIMER OVERFLOW
RATE/32 ( 2)
F
/64 ( 2)
TIMER OVERFLOW
RATE/32 ( 2)
10 - 9 BIT UART
11 - 9 BIT UART
SM2
IN MODES 2&3, ENABLES MULTIPROCESSOR
COMMUNICATION
RECEIVE ENABLE CONTROL BIT
IN MODES 2&3, 9TH BIT TRANSMITTED
IN MODES 2&3, 9TH BIT RECEIVED
TRANSMIT INTERRUPT FLAG
RECEIVE INTERRUPT FLAG
REN
TB8
RB8
TI
RI
SCON
SERIAL COMMUNICATIONS CONTROL REGISTER
T2EX
T2
P2
PORT2 REGISTER (ALSO A8 A15 & A16 A23)
TIMER/COUNTER 2 CAPTURE/RELOAD TRIGGER
TIMER/COUNTER 2 EXTERNAL INPUT
P0
PORT0 REGISTER (ALSO A0 A7 & D0 D7)
P1
PORT1 REGISTER (ANALOG & DIGITAL INPUTS)
PSMCON
POWER SUPPLY MONITOR
CONTROL REGISTER
PSMCON.7 (NOT USED)
PSMCON.6 PSM STATUS BIT
(1 = NORMAL/0 = FAULT)
PSMCON.5 PSM INTERRUPT BIT
PSMCON.4 TRIP POINT SELECT BITS
PSMCON.3 [4.63V, 4.37V, 3.08V, 2.93V, 2.63V]
PSMCON.2
PSMCON.1 AVDD/DVDD FAULT INDICATOR
(1 = ADD/0 = DVDD)
PSMCON.0 PSM POWERDOWN CONTROL
(1 = ON/0 = OFF)
PRE2
PRE1 TIMEOUT = [16, 32, 64, 128, 256, 512, 1024,
PRE0
2048] ms
WDR1 WATCHDOG TIMER REFRESH BITS
WDR2 SET SEQUENTIALLY TO REFRESH
WATCHDOG
WDS
WATCHDOG STATUS FLAG
WDE
WATCHDOG ENABLE
WATCHDOG TIMEOUT SELECTION BITS
WDCON
WATCHDOG TIME
CONTROL REGISTER
EADRL
DATA FLASH MEMORY
ADDRESS REGISTER
EDATA1, EDATA2, EDATA3, EDATA4
DATA FLASH DATA REGISTERS
01h READ
02h WRITE
03h (RESERVED)
04h VERIFY
05h ERASE
06h ERASE ALL
ECON
DATA FLASH MEMORY
COMMAND REGISTER
ETIM1, ETIM2, ETIM3
FLASH TIMING REGISTERS
í
29 8051
o ￠úàêó÷oíéáù
/
μ2á3yêyY′′￠÷
SFR
TH2, TL2
TIMER2 REGISTER
RCAP2H, RCAP2L
TIMER2 CAPTURE/RELOAD
TF2
EXF2
RCLK
OVERFLOW FLAG
EXTERNAL FLAG
RECEIVE CLOCK ENABLE
(0 = TIMER1 USED FOR RxD CLK)
TRANSMIT CLOCK ENABLE
(0 = TIMER1 USED FOR TxD CLK)
EXEN2 EXTERNAL ENABLE
(0 = IGNORE T2EX, 1 = CAP/RL)
TR2
RUN CONTROL (0 = STOP, 1 = RUN)
CNT2
TIMER/COUNTER SELECT
(0 = TIMER, 1 = COUNTER)
CAP2
CAPTURE/RELOAD SELECT
(0 = RELOAD, 1 = CAPTURE)
TCLK
T2CON
TIMER2 CONTROL REGISTER
TH0, TL0
TIMER0 REGISTERS
TH1, TL1
TIMER1 REGISTERS
TF1
TIMER1 OVERFLOW FLAG
(AUTO CLEARED ON VECTOR TO ISR)
TIMER1 RUN CONTROL (0 = OFF, 1 = RUN)
TIMER0 OVERFLOW FLAG
(AUTO CLEARED ON VECTOR TO ISR)
TIMER0 RUN CONTROL (0 = OFF, 1 = RUN)
EXTERNAL INT1 FLAG
(AUTO CLEARED ON VECTOR TO ISR)
IE1 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
EXTERNAL INT0 FLAG
(AUTO CLEARED ON VECTOR TO ISR)
IE0 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON
TIMER CONTROL REGISTER
PSI
PRIORITY OF ISI/ISPI
(SERIAL INTERFACE INTERRUPT)
PRIORITY OF ADCI (ADC INTERRUPT)
PRIORITY OF TF2/EXF2
(TIMER2 OVERFLOW INTERRUPT)
PRIORITY OF RI/TI (SERIAL PORT INTERRUPT)
PRIORITY OF TF1
(TIMER1 OVERFLOW INTERRUPT)
PRIORITY OF IE1 (EXTERNAL INT1)
PRIORITY OF TF0
(TIMER0 OVERFLOW INTERRUPT)
PRIORITY OF IE0 (EXTERNAL INT0)
PADC
PT2
PS
PT1
PX1
PT0
PX0
IP
INTERRUPT PRIORITY REGISTER
IE2.1
ENABLE PSMI
(POWER SUPPLY MONITOR INTERRUPT)
ENABLE ISPI/I2CI
(SERIAL INTERFACE INTERRUPT)
IE2.0
IE2
INTERRUPT ENABLE REGISTER #2
ENABLE INTURRUPTS
(0 = ALL INTERRUPTS DISABLED)
ENABLE ADCI (ADC INTERRUPT)
ENABLE TF2/EXF2
(TIMER2 OVERFLOW INTERRUPT)
ENABLE RI/TI (SERIAL PORT INTERRUPT)
ENABLE TF1 (TIMER1 OVERFLOW INTERRUPT)
ENABLE IE1 (EXTERNAL INTERRUPT 1)
ENABLE TFO (TIMER0 OVERFLOW INTERRUPT)
ENABLE IE0 (EXTERNAL INTERRUPT 0)
EADC
ET2
EA
ES
ET1
EX1
ET0
EX0
IE
INTERRUPT ENABLE REGISTER #1
TMOD.3/.7
TMOD.2/.6
TMOD.1/.5
TMOD.0/.4 [13 BIT T, 16 BIT T/C, 8 BIT T/C RELOAD,
2 8 BIT T]
(UPPER NIBBLE = TIMER1, LOWER NIBBLE = TIMER2)
GATE CONTROL BIT (0 = IGNORE INTx)
COUNTER/TIMER SELECT BIT (0 = TIMER)
TMOD
TIMER MODE REGISTER
ISPI
SPI INTERRUPT
(SET AT END OF SPI TRANSFER)
WCOL WRITE COLLISION ERROR FLAG
SPE
SPI ENABLE
(0 = DISABLE, ALSO ENABLES SPI)
SPIM
MASTER MODE SELECT (0 = SLAVE)
CPOL
CLOCK POLARITY SELECT
(0 = SCLK IDLES LOW)
CPHA
CLOCK PHASE SELECT
(0 = LEADING EDGE LATCH)
SPR1
SPI BITRATE SELECT BITS
SPR0
BITRATE = F
OSC
/ [4, 8, 32, 64]
SPIDAT
SPI DATA REGISTER
SPICON
SPI CONTROL REGISTER
MDO
MDE
MASTER MODE SDATA OUTPUT BIT
MASTER MODE SDATA OUTPUT
ENABLE
MASTER MODE SCLK BIT
MASTER MODE SDATA INPUT BIT
MASTER MODE SELECT
SERIAL PORT RESET
TRANSMISSION DIRECTION STATUS
SERIAL INTERFACE INTERRUPT
MCO
MDI
I
2
CM
I
2
CRS
I
2
CTX
I
2
CI
I2CCON
I
2
C CONTROL REGISTER
I2CADD
I
2
C ADDRESS REGISTER
I2CDAT
I
2
C DATA REGISTER
í
30
D ￠¨ê±÷ ￠
SPI
oí
I
2
C
SFR
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ADuC812 12-Bit ADC with Embedded FLASH MCU(12位8通道A/D轉(zhuǎn)換器)
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