參數(shù)資料
型號: ADUC7036CCPZ
廠商: Analog Devices Inc
文件頁數(shù): 5/132頁
文件大?。?/td> 0K
描述: IC MCU 96K FLASH DUAL 48LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 115°C
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
包裝: 托盤
ADuC7036
Rev. C | Page 102 of 132
WAKE-UP (WU) PIN
The wake-up (WU) pin is a high voltage GPIO controlled
through HVCON and HVDAT.
Wake-Up (WU) Pin Circuit Description
By default, the WU pin is configured as an output with an
internal 10 kΩ pull-down resistor and high-side FET driver.
In its default mode of operation, the WU pin is specified to
generate an active high system wake-up request by forcing the
external system WU bus high. User code can assert the WU
output by writing directly to HVCFG0[4].
Note that the output responds only after a 10 μs latency has elapsed;
this latency is inherent in a serial communication between the
HVCON or HVDAT MMR and the high voltage interface (see
The internal FET is capable of sourcing significant current;
therefore, substantial on-chip self-heating may occur if this
driver is asserted for a long time period. For this reason,
a monoflop (that is, a 1.3 sec timeout timer) is included.
By default, the monoflop is enabled and disables the wake-up
driver after 1.3 sec. It is possible to disable the monoflop through
HVCFG1[1]. If the wake-up monoflop is disabled, the wake-up
driver should be disabled after 1.3 sec.
The WU pin also features a short-circuit detection feature. When
the wake-up pin sources more than 100 mA typically for 400 μs,
a high voltage interrupt is generated, and HVMON[0] is set.
A thermal shutdown event disables the WU driver. The WU
driver must be reenabled manually after using HVCFG1[3]
after a thermal event.
The WU pin can be configured in I/O mode by writing a 1 to
HVCFG1[4]. In this mode, a rising or falling edge immediately
generates a high voltage interrupt. HVMON[7] directly reflects
the state of the external WU pin and indicates if the external
wake-up bus (including RLOAD = 1 kΩ, CLOAD = 91 nF, and RLIMIT =
39 Ω) is above or below a typical voltage of 3 V.
VDD
INTERNAL
SENSE
RESISTOR
SHORT-CIRCUIT
TRIP REFERENCE
SHORT-CIRCUIT
PROTECTION
OUTPUT CONTROL
HVMON[0]
NORMAL
HVCFG0[4]
NORMAL
HVMON[7]
400s
GLITCH
IMMUNITY
~1V
ENABLE
READBACK
HVCFG1[4]
INTERNAL
10k
RESISTOR
R1
6.6k
R2
3.3k
IO_VSS
6k
OPEN-CIRCUIT
DIAGNOSTIC
RESISTOR
EXTERNAL
WU PIN
EXTERNAL
WAKE-UP
BUS
CLOAD
91nF
RLOAD
1k
EXTERNAL
CURRENT-LIMIT
RESISTOR
39
HVCFG1[0]
07
47
4-
0
39
Figure 42. WU Circuit, Block Diagram
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