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參數(shù)資料
| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 39 of 92
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top 4 bits are the sign bits. The 12-bit result is placed from
Bit 16 to Bit 27 as shown in Figure 40. Again, it should be noted
that in fully differential mode, the result is represented in twos
complement format. In pseudo differential and single-ended
modes, the result is represented in straight binary format.
04
95
5-
01
4
SIGN BITS
12-BIT ADC RESULT
31
27
16 15
0
Figure 40. ADC Result Format
The same format is used in DACxDAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA
multiplied by the sampling frequency (in kHz). Figure 32 shows
the current consumption vs. the sampling frequency of the ADC.
Timing
Figure 41 gives details of the ADC timing. Users control the
ADC clock speed and on the number of acquisition clocks in
the ADCCON MMR. By default, the acquisition time is eight
clocks and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on temperature sensor, the
ADC acquisition time is automatically set to 16 clocks and the
ADC clock divider is set to 32. When using multiple channels
including the temperature sensor, the timing settings revert
back to the user-defined settings after reading the temperature
sensor channel.
0
4955
-0
15
ADC CLOCK
ACQ
BIT TRIAL
DATA
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
WRITE
CONVSTART
ADCBUSY
ADCDAT
Figure 41. ADC Timing
ADuC7019
The ADuC7019 is identical to the ADuC7020 except for one
buffered ADC channel, ADC3, and it has only three DACs. The
output buffer of the fourth DAC is internally connected to the
ADC3 channel as shown in Figure 42.
04
95
5-
0
16
1MSPS
12-BIT ADC
12-BIT
DAC
MUX
ADC3
ADC15
DAC3
ADuC7019
Figure 42. ADC3 Buffered Input
Note that the DAC3 output pin must be connected to a 10 nF
capacitor to AGND. This channel should be used to measure dc
voltages only. ADC calibration might be necessary on this channel.
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
ADCCON Register
Name
Address
Default Value
Access
ADCCON
0xFFFF0500
0x0600
R/W
ADCCON is an ADC control register that allows the
programmer to enable the ADC peripheral, select the mode
of operation of the ADC (either in single-ended mode, pseudo
differential mode, or fully differential mode), and select the
conversion type. This MMR is described in Table 15.
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