參數(shù)資料
型號： ADT7476AARQZ-R
廠商： ON Semiconductor
文件頁數(shù)： 54/66頁
文件大?。?/td> 945K
描述： IC REMOTE THERMAL CTLR 24QSOP
產(chǎn)品變化通告： MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標(biāo)準(zhǔn)包裝： 2,500
系列： dBCool®
功能： 風(fēng)扇控制，溫度監(jiān)控器
傳感器類型： 內(nèi)部和外部
感應(yīng)溫度： -40°C ~ 125°C
精確度： ±2.5%
拓?fù)洌?/td> ADC，比較器，風(fēng)扇速度計數(shù)器，多路復(fù)用器，寄存器庫
輸出類型： SMBus?
輸出警報： 無
輸出風(fēng)扇： 是
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 24-QSOP
包裝： 帶卷 (TR)
其它名稱： ADT7476AARQZ-R-ND
ADT7476AARQZ-ROSTR
ADT7476A
http://onsemi.com
54
Table 63. FAN TACH LIMIT REGISTERS (Note 1)
Register Address
R/W
Description
Power-On Default
0x54
R/W
TACH1 Minimum Low Byte
0xFF
0x55
R/W
TACH1 Minimum High Byte/Single-channel
ADC Channel Select
0xFF
0x56
R/W
TACH2 Minimum Low Byte
0xFF
0x57
R/W
TACH2 Minimum High Byte
0xFF
0x58
R/W
TACH3 Minimum Low Byte
0xFF
0x59
R/W
TACH3 Minimum High Byte
0xFF
0x5A
R/W
TACH4 Minimum Low Byte
0xFF
0x5B
R/W
TACH4 Minimum High Byte
0xFF
1.  Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 Lock bit has no effect on these registers.
Table 64. REGISTER 0x55  TACH1 MINIMUM HIGH BYTE (POWER-ON DEFAULT = 0xFF)
Bit No.
Mnemonic
R/W
Description
[4:0]
Reserved
Read-only
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are reserved. Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte.
[7:5]
SCADC
R/W
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are used to select the only channel from which the ADC will take measurements. Otherwise,
these bits represent Bits [7:5] of the TACH1 minimum high byte.
Table 65. PWM CONFIGURATION REGISTERS (Note 1)
Register Address
R/W
Description
Power-On Default
0x5C
R/W
PWM1 Configuration
0x62
0x5D
R/W
PWM2 Configuration
0x62
0x5E
R/W
PWM3 Configuration
0x62
Bit No.
Name
R/W
Description
[2:0]
SPIN
R/W
These bits control the startup timeout for PWMx. The PWM output stays high until two valid
TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan
TACH measurement directly after the fan startup timeout period, the TACH measurement
reads 0xFFFF and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum
high and low bytes contain 0xFFFF or 0x0000, the Interrupt Status Register 2 bit is not set,
even if the fan has not started.
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (Default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
[3]
RES
N/A
Reserved. Do not write to this bit.
[4]
INV
R/W
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for
100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle
corresponds to a logic low output.
[7:5]
BHVR
R/W
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 Temperature Controls PWMx (Automatic Fan Control Mode)
001 = Local Temperature Controls PWMx (Automatic Fan Control Mode)
010 = Remote 2 Temperature Controls PWMx (Automatic Fan Control Mode)
011 = PWMx Runs Full Speed (Default)
100 = PWMx Disabled
101 = Fastest Speed Calculated by Local and Remote 2 Temperature Controls PWMx
110 = Fastest Speed Calculated by All Three Temperature Channel Controls PWMx
111 = Manual Mode. PWM Current Duty Cycle Registers (0x30 to 0x32) Become Writable
1.  These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers fail.
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